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80C186EC 188EC 80L186EC 188EC
INSTRUCTION SET SUMMARY
Function
PROCESSOR CONTROL
CLC
Clear carry
e
Complement carry
CMC
e
STC
Set carry
e
CLD
Clear direction
e
STD
Set direction
e
CLI
Clear interrupt
e
STI
Set interrupt
e
HLT
Halt
e
WAIT
Wait
e
LOCK
Bus lock prefix
e
NOP
No Operation
e
Shaded areas indicate instructions not available in 8086 8088 microsystems
NOTE
Clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers
The Effective Address (EA) of the memory operand
is computed according to the mod and r m fields
if mod
11 then r m is treated as a REG field
e
if mod
00 then DISP
e
e
high are absent
if mod
01 then DISP
e
e
to 16-bits disp-high is absent
if mod
10 then DISP
e
e
if r m
000 then EA
e
e
if r m
001 then EA
e
e
if r m
010 then EA
e
e
if r m
011 then EA
e
e
if r m
100 then EA
e
e
if r m
101 then EA
e
e
if r m
110 then EA
e
e
if r m
111 then EA
e
e
DISP follows 2nd byte of instruction (before data if
required)
except if mod
00 and r m
e
disp-high disp-low
EA calculation time is 4 clock cycles for all modes
and is included in the execution times given whenev-
er appropriate
56
(Continued)
1 1 1 1 1 0 0 0
1 1 1 1 0 1 0 1
1 1 1 1 1 0 0 1
1 1 1 1 1 1 0 0
1 1 1 1 1 1 0 1
1 1 1 1 1 0 1 0
1 1 1 1 1 0 1 1
1 1 1 1 0 1 0 0
1 0 0 1 1 0 1 1
1 1 1 1 0 0 0 0
1 0 0 1 0 0 0 0
(TTT LLL are opcode to processor extension)
0 disp-low and disp-
disp-low sign-extended
disp-high disp-low
(BX)
(SI)
DISP
a
a
(BX)
(DI)
DISP
a
a
(BP)
(SI)
DISP
a
a
(BP)
(DI)
DISP
a
a
(SI)
DISP
a
(DI)
DISP
a
(BP)
DISP
a
(BX)
DISP
a
110 then EA
e
e
Format
Segment Override Prefix
0 0 1 reg 1 1 0
reg is assigned according to the following
reg
00
01
10
11
REG is assigned according to the following table
16-Bit (w
e
000 AX
001 CX
010 DX
011 BX
100 SP
101 BP
110 SI
111 DI
The physical addresses of all operands addressed
by the BP register are computed using the SS seg-
ment register The physical addresses of the desti-
nation operands of the string primitive operations
(those addressed by the DI register) are computed
using the ES segment which may not be overridden
80C186EC
80C188EC
Clock
Clock
Comments
Cycles
Cycles
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
6
6
if TEST
2
2
3
3
Segment
Register
ES
CS
SS
DS
1)
8-Bit (w
0)
e
000 AL
001 CL
010 DL
011 BL
100 AH
101 CH
110 DH
111 BH
0
e
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