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80C186EC 188EC 80L186EC 188EC
Pin
Pin Name
Type
RD
O
WR
O
READY
I
(Note 1)
DEN
O
DT R
O
LOCK
I O
HOLD
I
HLDA
O
NCS
O
ERROR
I
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
12
Table 2 Pin Descriptions (Continued)
Input
Output
Type
States
H(Z)
ReaD output signals that the accessed memory or I O
device should drive data information onto the data bus
R(Z)
I(1)
P(1)
H(Z)
WRite output signals that data available on the data bus are
to be written into the accessed memory or I O device
R(Z)
I(1)
P(1)
A(L)
READY input to signal the completion of a bus cycle READY
must be active to terminate any 80C186EC bus cycle unless
S(L)
it is ignored by correctly programming the Chip-Select unit
H(Z)
Data ENable output to control the enable of bi-directional
transceivers in a buffered system DEN is active only when
R(Z)
data is to be transferred on the bus
I(1)
P(1)
H(Z)
Data Transmit Receive output controls the direction of a bi-
directional buffer in a buffered system
R(Z)
I(X)
P(X)
A(L)
H(Z)
LOCK output indicates that the bus cycle in progress is not
interruptable The processor will not service other bus
R(Z)
requests (such as HOLD) while LOCK is active This pin is
I(X)
configured as a weakly held high input while RESIN is active
P(X)
and must not be driven low
A(L)
HOLD request input to signal that an external bus master
wishes to gain control of the local bus The processor will
relinquish control of the local bus between instruction
boundaries that are not LOCKed
H(1)
HoLD Acknowledge output to indicate that the processor
has relinquished control of the local bus When HLDA is
R(0)
asserted the processor will (or has) floated its data bus and
I(0)
control signals allowing another bus master to drive the
P(0)
signals directly
H(1)
Numerics Coprocessor Select output is generated when
acessing a numerics coprocessor This signal does not exist
R(1)
on the 80C188EC 80L188EC
I(1)
P(1)
A(L)
ERROR input that indicates the last numerics processor
extension operation resulted in an exception condition An
interrupt TYPE 16 is generated if ERROR is sampled active
at the beginning of a numerics operation Systems not using
an 80C187 must tie ERROR to V
exist on the 80C188EC 80L188EC
Pin Description
This signal does not
CC
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