Intel 80C186EC Manual page 49

80C186EC 188EC 80L186EC 188EC
272434 –23
NOTES
1 READY must be low by either edge to cause a wait state
2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles
Pin names in parentheses apply to 80C188EC 80L188EC
Figure 24 READY Cycle Waveforms
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