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80C186EC 188EC 80L186EC 188EC
Pin
Pin Name
Type
V
P
CC
V
G
SS
CLKIN
I
OSCOUT
O
CLKOUT
O
RESIN
I
RESOUT
O
PDTMR
I O
NMI
I
TEST BUSY
I
(TEST)
A19 S6 ONCE
I O
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
10
Table 2 Pin Descriptions
Input
Output
Type
States
POWER
GROUND
A(E)
CLocK INput is the external clock input An external
oscillator operating at two times the required processor
operating frequency can be connected to CLKIN For
crystal operation CLKIN (along with OSCOUT) are the
crystal connections to an internal Pierce oscillator
H(Q)
OSCillator OUTput is only used when using a crystal to
generate the internal clock OSCOUT (along with CLKIN)
R(Q)
are the crystal connections to an internal Pierce oscillator
I(Q)
This pin can not be used as 2X clock output for non-
P(X)
crystal applications (i e this pin is not connected for non-
crystal applications)
H(Q)
CLocK OUTput provides a timing reference for inputs and
outputs of the processor and is one-half the input clock
R(Q)
(CLKIN) frequency CLKOUT has a 50% duty cycle and
I(Q)
transitions every falling edge of CLKIN
P(X)
A(L)
RESet IN causes the processor to immediately terminate
any bus cycle in progress and assume an initialized state
All pins will be driven to a known state and RESOUT will
also be driven active The rising edge (low-to-high)
transition synchronizes CLKOUT with CLKIN before the
processor begins fetching opcodes at memory location
0FFFF0H
H(0)
RESet OUTput that indicates the processor is currently in
the reset state RESOUT will remain active as long as
R(1)
RESIN remains active
I(0)
P(0)
A(L)
H(WH)
Power-Down TiMeR pin (normally connected to an
external capacitor) that determines the amount of time the
R(Z)
processors waits after an exit from Powerdown before
P(WH)
resuming normal operation The duration of time required
I(WH)
will depend on the startup characteristics of the crystal
oscillator
A(E)
Non-Maskable Interrupt input causes a TYPE-2 interrupt
to be serviced by the CPU NMI is latched internally
A(E)
TEST is used during the execution of the WAIT instruction
to suspend CPU operation until the pin is sampled active
(LOW) TEST is alternately known as BUSY when
interfacing with an 80C187 numerics coprocessor
(80C186EC only)
A(L)
H(Z)
This pin drives address bit 19 during the address phase of
the bus cycle During T2 and T3 this pin functions as
R(WH)
status bit 6 S6 is low to indicate CPU bus cycles and high
I(0)
to indicate DMA or refresh bus cycles During a processor
P(0)
reset (RESIN active) this pin becomes the ONCE input
pin Holding this pin low during reset will force the part into
ONCE Mode
Pin Description
5V
10% power supply connection
a
g
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