Supermicro X10DRG-O+-CPU User Manual page 11

X10DRG-O+-CPU/X10DRG-OT+-CPU Layout
JPW22
JPW21
CLOSE 1st
JPB1
J1
CPU2
JPME2
JBR1
JWD1
JSPK1
JF1
1
JF1
PWR PS UID NIC NIC HDD PWR
RST NMI
ON FAIL LED 2 1 LED LED
Notes:
•
For the latest CPU/memory updates, please refer to our website at http://www.
supermicro.com/products/motherboard/ for details.
•
See Chapter 2 for detailed information on jumpers, I/O ports and JF1 front
panel connections.
•
" " indicates the location of Pin 1.
•
Jumpers/LED indicators not indicated are for internal testing only.
•
Use only the correct type of onboard CMOS battery as specifi ed by the manufac-
turer. Do not install the onboard battery upside down to avoid possible explosion.
IPMI_LAN
USB5/6(3.0)
VGA
LAN2 LAN1
BMC
LAN
CTRL
PCH
JBT1
USB2/3
1
X10DRG-O+-CPU
REV: 1.00
BAR CODE 1G/10G MAC CODE
BIOS LICENSE IPMI CODE
10G SAN MAC
OPEN 1st
1-3
Chapter 1: Overview
JPW23
BT1
CLOSE 1st
CPU1
OPEN 1st
JPP2
JITP1
JPP1
JPW24
JPW5
I-SGPIO2
I-SGPIO1
LD1
LD2