Post Progress And Error Reporting - Sun Microsystems Sun Blade 150 Service Manual

CODE EXAMPLE 3-2
Copyright 1998-2002 Sun Microsystems, Inc.
OpenBoot 4.6, 1024 MB memory installed, Serial #51602330.
Ethernet address 0:3:ba:13:63:9a, Host ID: 8313639a.
3.7

POST Progress and Error Reporting

POST progress indications are visible when a TTY-type terminal or a TIP line is
connected between the serial port of the tested system and a second Sun
workstation.
In most cases, POST also attempts to send a failure message to the POST monitoring
system.
Note – The system does not automatically boot if a critical component fails the
POST test. The system will halt at the system prompt to alert the user to a failure.
CODE EXAMPLE 3-3
Processor Module Identification
UltraSPARC-IIe Version 1.1
Init POST BSS
Init System BSS
NVRAM Tests
NVRAM Battery Detect Test
NVRAM Scratch Addr Test
NVRAM Scratch Data Test
DMMU TLB Tags
DMMU TLB Tag Access Test
DMMU TLB RAM
DMMU TLB RAM Access Test
Probe Ecache
Probe Ecache
Ecache Size = 0x00080000 bytes = 512 KBytes
Measure CPU Clock
Initializing Southbridge
Nominal CPU speed is 650 MHz
All CPU Basic Tests
diag-level Variable Set to min
shows the typical appearance of an error message.
CODE EXAMPLE 3-3
Typical POST Error Message: DIMM Failure
(Continued)
All rights reserved.
Chapter 3 Power-On Self-Test 3-25