Sun Microsystems Sun Blade 150 Service Manual page 44

CODE EXAMPLE 3-1
All Basic Cache Tests
MCU Control & Status Regs Init
Ecache Tests
Memory Init
3-8 Sun Blade 150 Service Manual • June 2002
diag-level Variable Set to max
DMMU Primary Context Reg Test
DMMU Secondary Context Reg Test
DMMU TSB Reg Test
DMMU Tag Access Reg Test
DMMU VA Watchpoint Reg Test
DMMU PA Watchpoint Reg Test
IMMU TSB Reg Test
IMMU Tag Access Reg Test
Dcache RAM Test
Dcache Tag Test
Icache RAM Test
Icache Tag Test
Icache Next Test
Icache Predecode Test
Initializing Memory and MC registers
DIMM 0: 256 MBytes = 0x10000000 bytes
DIMM 1: 256 MBytes = 0x10000000 bytes
DIMM 2: 256 MBytes = 0x10000000 bytes
DIMM 3: 256 MBytes = 0x10000000 bytes
Found 4 DIMMs in bank 0
Bank 0: 1024 MBytes
DIMM0 is a 32M x 8 device
DIMM1 is a 32M x 8 device
DIMM2 is a 32M x 8 device
DIMM3 is a 32M x 8 device
MC0 = 0x00000000.96a0cf06
MC1 = 0x00000000.80008000
MC2 = 0x00000000.cff0eeee
MC3 = 0x00000000.00600b5f
CPU MODULE upa_config is 0x0000003a.00000000
Displacement Flush Ecache
Ecache RAM Addr Test
Ecache Tag Addr Test
Ecache RAM Test
Ecache Tag Test
Malloc Post Memory
Memory Addr Check w/o Ecache
Load Post In Memory
Run POST from MEM
(Continued)