Mitsubishi Electric MELSEC iQ-R Series Safety Function Block Reference page 99

Typical timing diagram
■ For M+SF_TSSEN_R
i_bActivate
i_bS_OSSD_In
i_bStartTest
i_dTestTimer1
i_dTestTimer2
i_bNoExternalTest
i_bS_StartReset
i_bS_AutoReset
i_bReset
o_bReady
o_bS_OSSD_Out
o_bTestPossible
o_bS_TestOut
o_bTestExecuted
o_bError
0000H 8001H
o_wDiagCode
A program operation is suspended while the operation status of the CPU module is in STOP or PAUSE. Consequently,
measurement of the i_dTestTimer1 and i_dTestTimer2 elapsed time is stopped.
Error behavior
In the event of an error, the output signals behave as listed below.
Output signal
o_bReady
o_bS_OSSD_Out
o_bS_TestOut
o_bTestPossible
o_bTestExecuted
o_bError
The C007H output signal is excluded from the signals in the list. For the output signal status and corrective actions of C007H,
see the following.
Page 98 List of error codes
8010H 8020H 8030H 8000H 8012H 8013H 8012H 8013H
Status
ON
OFF
ON
OFF
OFF
ON
4 SAFETY FB SPECIFICATIONS
8000H 0000H
4.14 M+SF_TSSEN_R
4
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