Table 44. Diagnostic Led Post Code Decoder - Intel S5000VCL Technical Product Specification

Intel Server Board S5000VCL TPS
®
Diagnostic LED Decoder
Checkpoint G=Green, R=Red, A=Amber
MSB
Host Processor
0x10h OFF OFF
0x11h OFF OFF
0x12h OFF OFF
0x13h OFF OFF
Chipset
0x21h Off Off
Memory
0x22h Off Off
0x23h Off Off
0x24h Off G
0x25h Off G
0x26h Off G
0x27h Off G
0x28h G Off
PCI Bus
0x50h Off R
0x51h Off R
0x52h Off R
0x53h Off R
0x54h Off A
0x55h Off A
0x56h Off A
0x57h Off A
USB
0x58h G R
0x59h G R
ATA/ATAPI/SATA
0x5Ah G R
0x5Bh G R
SMBUS
0x5Ch G A
0x5Dh G A
Local Console
0x70h Off R
0x71h Off R
0x72h Off R
Remote Console
0x78h G R
0x79h G R
0x7Ah G R
Revision 2.3

Table 44. Diagnostic LED POST Code Decoder

LSB
OFF R Power-on initialization of the host processor (bootstrap processor)
OFF A Host processor cache initialization (including AP)
G R Starting application processor initialization
G A SMM initialization
R G Initializing a chipset component
A Off Reading configuration data from memory (SPD on DIMM)
A G Detecting presence of memory
R Off Programming timing parameters in the memory controller
R G Configuring memory parameters in the memory controller
A Off Optimizing memory controller settings
A G Initializing memory, such as ECC init
R Off Testing memory
Off R Enumerating PCI busses
Off A Allocating resources to PCI busses
G R Hot Plug PCI controller initialization
G A Reserved for PCI bus
Off R Reserved for PCI bus
Off A Reserved for PCI bus
G R Reserved for PCI bus
G A Reserved for PCI bus
Off R Resetting USB bus
Off A Reserved for USB devices
G R Resetting PATA/SATA bus and all devices
G A Reserved for ATA
Off R Resetting SMBUS
Off A Reserved for SMBUS
R R Resetting the video controller (VGA)
R A Disabling the video controller (VGA)
A R Enabling the video controller (VGA)
R R Resetting the console controller
R A Disabling the console controller
A R Enabling the console controller
Intel order number: D64569-007
Appendix D: POST Code Diagnostic LED Decoder
Description
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