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Pin No.
Pin Name
27
VDD5V
28~34
MA<2~8>
MA<0~1>
37~38
39
CS#
40
WE#
41
RAS#
42
DAEMP
43,60,69,92
VDD
45
PCMCLK
46
PCMWS
47
PCMSD
48
EMP
49
VSYNC#
50
HSYNC#
CSYNC
51
PD<4~7>
52~55
57
VCLK
PD<2~3>
58~59
PD<0~1>
61~62
63
BLANK#
64,71,75,93
VSS
65~68,70
SD<0~3,4>
72~73
SD<5~7>
76
MCLK
77
BUSY#
78
ALE
79
SO
80
IRQ#
81
WR#
82
RD#
SA<5~7>
83~85
86
VDD5V
87~91
SA<0~4>
94
ACLK
95
ACLKO
96
CDCLK
97
CDSD
98
CDWS
99
C2PO
100
RESET
type
5V power supply
O
DRAM address bus
O
DRAM address bus
Column address strobe output, falling edge active
O
O
Write enableoutput, active LOW to indicate write operation to
DRAM
O
Row address strobe output, falling edge active
I
DA emphasis input, active HIGH
3.3V power supply
O
Audio PCM clock output
PCM channel word selector, active HIGH, programmable
O
Audio PCM serial data output
O
O
Audio emphasis flag, active HIGH
Vertical synch, active LOW, input/output programmable,
I/O
default in INPUT state
Horizontal sync, active LOW, input/output programmable,
I/O
default in INPUT state
O
Composite sync signal, active LOW
O
Pixel Data bus
I/O
Video clock, usually 27MHz for TV scan, twice the luminance rate,
input/output programmable, default in INPUT state
O
Pixel Data bus
O
Pixel Data bus
O
Composite blank, active LOW
0V ground
System data bus
I/O
I/O
System data bus
I
Main clock input, typically 40.5MHz
O
Bus BUSY, LOW indicates bus busy, open
active HIGH, address latch enable for 8051
I
O
Address select output, valid from IOAR+10h to IOAR+2fh
(total 32 byteaddresses), active LOW
O
Interrupt request output, active when an interrupt event is triggered,
active LOW
I
write enable, active LOW
I
Read enable, active LOW
I
System address bus
3.3V power supply
I
System address bus
I
Optional secondary clock for audio sampling rate, PCM clock
O
ACLK output, ACLK and ACLKO are used for crystal input pins
I
CD bit clock input
I
CD serial data input
I
CD data word selector
CD data byte erasure flag
I
I
System reset, active HIGH
MX-G68V/MX-G65V
Function
HSYNC# are in input state
(2/2)
KB9226
1-49
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