JVC RX-DV31SL Service Manual page 52

Pin No. Symbol
92 SSPOUT0/DTR0
93 TXD0
94 RXD0
95 CTS0
96 RTS0
97 VSSIO
98 CXI
99 CXO
100 OSCVSS
101 OSCVDD
102 MVCKVDD
103 SCEN
104 MVCKVSS
105 ACLKVSS
106 SCMD
107 ACLKVDD
108 VDDDAC
109 VSSDAC
110 DAC3
111 IOM
112 DAC2
113 VAA3
114 DAC1
115 VSSA
116 VREF
117 NC
118 DAC0
119 RSET
120 COMP
121 VSS
122 VIOCLK
123 VSYNC
124 HSYNC
125 VDDIO
126-131 VIO
132 VSSIO
133, 134 VIO
135 VDD
136-139 AD
140 VDDIO
141-144 AD
145 PWE
146 AD
147 VSSIO
148-153 AD
154 VDDIO
155 AD
156 PWE
157, 158 AD
159 VDD
160 SCLK
1-52 (No.22023)
I/O
I/O SSP0 data out or UART0 data-terminal-ready signal
I/O UART0 serial data output to an external serial device
I UART0 serial data input from external serial device
I/O UART0 clear-to-send signal
I/O UART0 request-to-send signal
I/O pad ground
I Crystal input pin for on-chip oscillator or system input clock
O Crystal output pin for on-chip oscillator
Oscillator ground
Oscillator power
Main and video clock PLL power
I Scan chain test enable
Main and video clock PLL ground
Audio clock PLL ground
I Scan chain test mode
Audio clock PLL power
DAC digital power
DAC digital ground
O Video DAC3 output
O Cascaded DAC differential output used to dump current into external resistor for power
O Video DAC2 output
DAC analog power
O Video DAC1 output
DAC analog ground
I Input voltage reference for output DACs
Unused
O Video DAC output
O Current setting resistor of output DACs
O Compensation capacitor connection
Core and Ring ground
I/O VCLK input/output for video I/O port function
I/O Bi-directional VSYNC signal for devices
I/O Bi-directional HSYNC signal for devices
I/O pad power =3.3V
I/O Bi-directional digital video port data bus
I/O pad ground
I/O Bi-directional digital video port data bus
Core power =1.8V
I/O Multipleced address/data bus
I/O pad power =3.3V
I/O Multipleced address/data bus
I/O Byte write enable for FLASH, EEPROM, SRAM or peripherals
I/O Multipleced address/data bus
I/O pad ground
I/O Multipleced address/data bus
I/O pad power =3.3V
I/O Multipleced address/data bus
I/O Byte write enable for FLASH, EEPROM, SRAM or peripherals
I/O Multipleced address/data bus
Core power =1.8V
O External bus clock used for programmable host bus peripherals
Function