JVC RX-DV31SL Service Manual page 49

6.28 MN102L62GLF3 (IC401) : Unit CPU
• Pin layout
1
25
• Pin function
Pin No. Symbol I/O
1 WAIT I Micro computer wait signal input
2 RE O Read enable
3 /SPMUTE O Spindle muting output to IC251
4 WEN O Write enable
5 /LMMUTE - Not connect
6 CS1 O Chip select for ODC
7 CS2 - Chip select for ZIVA
8 HDTYPE O HD TYPE selection
9 /DRVMUTE O Driver mute
10 SBRK O SP motor brake control
11 LSIRST O LSI reset
12 WOR0 O Bus selection input
13-16 A0-A3 O Address bus (0-3) for CPU
17 VDD - Power supply
18 SYSCLK - System clock signal output
19 VSS - Ground
20 XI - Not use (Connect to VSS)
21 XO - Not connect
22 VDD - Power supply
23 OSCI I Clock signal input (13.5MHz)
24 OSCO O Clock signal output (13.5MHz)
25 MODE I CPU mode selection input
26-33 A4-A11 O Address bus (4-11) for CPU
34 VDD - Power supply
35-40 A12-A17 O Address bus (12-17) for CPU
41 A18 - Address bus 18 for CPU
42 A19 - Address bus 19 for CPU
43 VSS - Ground
44 A20 - Address bus 20 for CPU
45 DISCSTP O DISC STOP control
46 HAGUP O H/A gain control
47 TCLOSE - Not connect.
48 WOBBLEFIL - Not connect.
49 /HFMON I HF monitor
50 TRVSW I Detection switch of traverse in-
100 76
75
51
26 50
Function
(Not connect.)
(Not connect.)
(Not connect.)
(Not connect.)
(Not connect.)
( Not connect.)
side
Pin No. Symbol I/O
51 SWUPDN - Not connect.
52 MECHA_H/V I Disc detection
53 DISCSET O Serial enable signal for ADSC
54 VDD - Power supply
55 FEPEN O Serial enable signal for FEP
56 SLEEP O Standby signal for FEP
57 BUSY - Not connect.
58 REQ O Communication request
59 - Connect to TP405 (REQ)
60 - Not connect.
61 VSS - Ground
62 EPCS O EEPROM chip select
63 EPSK O EEPROM clock
64 EPDI I EEPROM data input
65 EPDO O EEPROM data output
66 VDD - Power supply
67 SCLKO I Communication clock
68 S2UTD I Communication input data
69 U2SDT O Communication output data
70 CPSCK O Clock for ADSC serial
71 P74/SBI1 - Connect to VSS
72 SDOUT O ADSC serial data output
73 - Not use.
74 - Not use.
75 NMI - Not use.
76 ADSCIRQ I Interrupt input of ADSC
77 ODCIRQ I Interrupt input of ODC
78 DECIRQ I Interrupt input of ZIVA
79 CSSIRQ I Interrupt input of SODC
80 ODCIRQ2 I Interruption of system control
81 ADSEP I Address data selection input
82 RST I Reset input
83 VDD - Power supply
84-91 TEST1-TEST 8 I Test signal (1-8) input
92 VSS - Ground
93-100 D0-7 I/O Data bus (0-7) of CPU
Function
(Pull-up to power supply)
(Pull-up to power supply)
(Pull-up to power supply)
(Pull-up to power supply)
(Not connect.)
(No.22023)1-49