JVC RX-DV31SL Service Manual page 37

Pin No. Symbol
24,25~27 A10,A0 - A2
28 DQM2
29 VDD
30 N.C
31 DQ16
32 VSSQ
33,34 DQ17,DQ18
35 VDDQ
36,37 DQ19,DQ20
38 VSSQ
39,40 DQ21,DQ22
41 VDDQ
42 DQ23
43 VDD
44 VSS
45 DQ24
46 VSSQ
47,48 DQ25,DQ26
49 VDDQ
50,51 DQ27,DQ28
52 VSSQ
53,54 DQ29,DQ30
55 VDDQ
56 DQ31
57 N.C
58 VSS
59 DQM3
60~66 A3 - A9
67 CKE
68 CLK
69,70 N.C
71 DQM1
72 VSS
73 N.C
74 DQ8
75 VDDQ
76,77 DQ9,DQ10
78 VSSQ
79,80 DQ11,DQ12
81 VDDQ
82,83 DQ13,DQ14
84 VSSQ
85 DQ15
86 VSS
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Power for the input buffers and core logic.
This pin is recommended to be left no connection on the device.
Data input/output are multiplexed on the same pin.
Isolated ground for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated ground for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply for the output buffers to provide improved noise immunity.
Data input/output are multiplexed on the same pin.
Power for the input buffers and core logic.
Ground for the input buffers and core logic.
Data input/output are multiplexed on the same pin.
Isolated ground for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated ground for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply for the output buffers to provide improved noise immunity.
Data input/output are multiplexed on the same pin.
This pin is recommended to be left no connection on the device.
Ground for the input buffers and core logic.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 - RA10, Column address : CA0 - CA7
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Active on the positive going edge to sample all inputs.
This pin is recommended to be left no connection on the device.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Ground for the input buffers and core logic.
This pin is recommended to be left no connection on the device.
Data input/output are multiplexed on the same pin.
Isolated power supply for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated ground for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated ground for the output buffers to provide improved noise immunity.
Data input/output are multiplexed on the same pin.
Ground for the input buffers and core logic.
Function
(No.22023)1-37