JVC RX-DV31SL Service Manual page 39

6.16 LM1117MP1.8-X (IC511) : Regulator
• Pin layout
6.17 LP61L1024S-12-X (IC641) : SRAM
• Pin layout
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O1 13
I/O2 14
I/O3 15
VSS 16
Top view
32 VDD
31 A15
30 NC(CE2)
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS1
21 I/O8
20 I/O7
19 I/O6
18 I/O5
17 I/O4
• Block diagram
Thermal
GND (FIXED OUTPUT)
ADJ.(ADJUSTABLE OUTPUT)
• Block diagram
V
DD
Vss
A0
DECODER
A16
CS2
CS1
CONTROL
OE
WE
• Pin function
SYMBOL DESCRIPTION
A0 - A16 Address Input
I/O1 - I/O8 Data Input/Output
CS1, CS2 Chip Select Inputs
WE Write Enable Input
OE Output Enable Input
VDD Power Supply
Vss Ground
NC No Connection
V
Limit
Current
Limit
V
Substrate
CORE
ARRAY
I/O1
DATA I/O
I/O8
(No.22023)1-39
IN
OUT