JVC RX-DV31SL Service Manual page 36

6.14 K4S643232E-TC60 (IC505) : 512K x 32 bit x 4 banks synchronous DRAM
• Pin layout
86
1
• Block diagram
CLK
ADD
• Pin function
Pin No. Symbol
1 VDD
2 DQ0
3 VDDQ
4,5 DQ1,DQ2
6 VSSQ
7,8 DQ3,DQ4
9 VDDQ
10,11 DQ5,DQ6
12 VSSQ
13 DQ7
14 N.C
15 VDD
16 DQM0
17 WE
18 CAS
19 RAS
20 CS
21 N.C
22,23 BA0,BA1
1-36 (No.22023)
44
43
Bank Select
LCKE LCAS
LRAS LCBR LWE
Timing Register
CLK CKE CS
Power for the input buffers and core logic.
Data input/output are multiplexed on the same pin.
Isolated power supply for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated ground for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated ground for the output buffers to provide improved noise immunity.
Data input/output are multiplexed on the same pin.
This pin is recommended to be left no connection on the device.
Power for the input buffers and core logic.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM.
This pin is recommended to be left no connection on the device.
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Data Input Register
512K x 32
512K x 32
512K x 32
512K x 32
Column Decoder
Latency & Burst Length
Programming Register
LWCBR
RAS CAS WE DQM
Function
LWE
LDQM
DQi
LDQM