Ddriii Cha So-Dimm_0 - Clevo P170EM Service Manual

DDRIII CHA SO-DIMM_0

Channel A SO-DIMM 0
5,11
Layout Note:
signal/space/signal:
8 / 4 / 8
5,11
5,11
5,11
5
5
5 M_A_CLK_DD R0
5 M_A_CLK_DD R#0
5 M_A_CLK_DD R1
5 M_A_CLK_DD R#1
5
5
5,11
5,11
5,11
11,12,13,21
11,12,13,21
5
5
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
5,11
3.3VS
5,11
RN 4
10K_8P4R_04
1 8 CHA_SA1_DIM1
C HA_SA1_D IM1 11
2 7 CHA_SA0_DIM1
C HA_SA0_D IM1 11
3 6 CHA_SA1_DIM0
4 5 CHA_SA0_DIM0
D05
1.5V
C709¤W¥ó
C327 C709 C696
+ +
220u_4V_V_A 220u_4V_V_A 10u_6.3V_X5R _06
1.5V
C663 C576 C667
0.1u_10V_X5R_04 0.1u_10V_X5R _04
0.1u_10V_X5R_04
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CHANGE TO STANDARD
JD IMM3A
M_A_A[15:0]
M_A_A0 98 5 M_A_DQ0
A0 DQ0
M_A_A1 97 7 M_A_DQ1
A1 DQ1
M_A_A2 96 15 M_A_DQ2
A2 DQ2
M_A_A3 95 17 M_A_DQ3
A3 DQ3
M_A_A4 92 4 M_A_DQ4
A4 DQ4
M_A_A5 91 6 M_A_DQ5
A5 DQ5
M_A_A6 90 16 M_A_DQ6
A6 DQ6
M_A_A7 86 18 M_A_DQ7
A7 DQ7
M_A_A8 89 21 M_A_DQ8
A8 DQ8
M_A_A9 85 23 M_A_DQ9
A9 DQ9
M_A_A10 107 33 M_A_DQ10
A10/AP D Q10
M_A_A11 84 35 M_A_DQ11
A11 D Q11
M_A_A12 83 22 M_A_DQ12
A12/BC# D Q12
M_A_A13 119 24 M_A_DQ13
A13 D Q13
M_A_A14 80 34 M_A_DQ14
A14 D Q14
M_A_A15 78 36 M_A_DQ15
A15 D Q15
39 M_A_DQ16
D Q16
109 41 M_A_DQ17
M_A_BS0
BA0 D Q17
108 51 M_A_DQ18
M_A_BS1
BA1 D Q18
79 53 M_A_DQ19
M_A_BS2
BA2 D Q19
114 40 M_A_DQ20
M_A_C S#0 S0# D Q20
121 42 M_A_DQ21
M_A_C S#1 S1# D Q21
101 50 M_A_DQ22
C K0 D Q22
103 52 M_A_DQ23
C K0# D Q23
102 57 M_A_DQ24
C K1 D Q24
104 59 M_A_DQ25
C K1# D Q25
73 67 M_A_DQ26
M_A_C KE0 C KE0 D Q26
74 69 M_A_DQ27
M_A_C KE1 C KE1 D Q27
115 56 M_A_DQ28
M_A_CAS# C AS# D Q28
110 58 M_A_DQ29
M_A_RAS#
R AS# D Q29
113 68 M_A_DQ30
M_A_WE#
WE# D Q30
CHA_SA0_D IM0 197 70 M_A_DQ31
SA0 D Q31
CHA_SA1_D IM0 201 129 M_A_DQ32
SA1 D Q32
202 131 M_A_DQ33
SMB_C LK SCL D Q33
200 141 M_A_DQ34
SMB_D ATA SDA D Q34
143 M_A_DQ35
D Q35
116 130 M_A_DQ36
M_A_ODT0 ODT0 D Q36
120 132 M_A_DQ37
M_A_ODT1 ODT1 D Q37
140 M_A_DQ38
D Q38
11 142 M_A_DQ39
D M0 D Q39
28 147 M_A_DQ40
D M1 D Q40
46 149 M_A_DQ41
D M2 D Q41
63 157 M_A_DQ42
D M3 D Q42
136 159 M_A_DQ43
D M4 D Q43
153 146 M_A_DQ44
D M5 D Q44
170 148 M_A_DQ45
D M6 D Q45
187 158 M_A_DQ46
D M7 D Q46
160 M_A_DQ47
M_A_D QS[7:0] D Q47
M_A_DQS0 12 163 M_A_DQ48
D QS0 D Q48
M_A_DQS1 29 165 M_A_DQ49
D QS1 D Q49
M_A_DQS2 47 175 M_A_DQ50
D QS2 D Q50
M_A_DQS3 64 177 M_A_DQ51
D QS3 D Q51
M_A_DQS4 137 164 M_A_DQ52
D QS4 D Q52
M_A_DQS5 154 166 M_A_DQ53
D QS5 D Q53
M_A_DQS6 171 174 M_A_DQ54
D QS6 D Q54
M_A_DQS7 188 176 M_A_DQ55
D QS7 D Q55
181 M_A_DQ56
M_A_DQS#[7:0] D Q56
M_A_DQS#0 10 183 M_A_DQ57
D QS0# D Q57
M_A_DQS#1 27 191 M_A_DQ58
D QS1# D Q58
M_A_DQS#2 45 193 M_A_DQ59
D QS2# D Q59
M_A_DQS#3 62 180 M_A_DQ60
D QS3# D Q60
M_A_DQS#4 135 182 M_A_DQ61
D QS4# D Q61
M_A_DQS#5 152 192 M_A_DQ62
D QS5# D Q62
M_A_DQS#6 169 194 M_A_DQ63
D QS6# D Q63
M_A_DQS#7 186
D QS7#
DDRSK-20401-TR5B
C695 C694 C577 C 578 C579 C580 C639
10u_6.3V_X5R_06 1u_6.3V_X5R_04 1u_6.3V_X5R _04
10u_6.3V_X5R_06 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04
C638 C666 C595 C 640 C664 C665 C593
0.1u_10V_X5R_04 0.1u_10V_X5R_04 0.1u_10V_X5R_04
0.1u_10V_X5R_04 0.1u_10V_X5R_04 0.1u_10V_X5R_04 0.1u_10V_X5R _04
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M_A_DQ[63:0] 5,11
D03 modify 3.3VS
2.2u_16V_X5R_06 20mils
change to 1u_6.3V_Y5V_04
bug 76 C575
D05
C574
1u_6.3V_X5R _04 0.1u_16V_Y 5V_04
3.3VS
R442 * 10K_04
11,12,13 TS#_DIMM0_1
4,11,12,13 DD R3_DRAMRST#
C325 2.2u_6.3V_Y 5V_06
C330 0.1u_16V_Y 5V_04
7,11 MVR EF_DQ_DIMMA
MVR EF_CA_DIMMA_R
R441 *0_04
7 MVR EF_CA_DIMMA
C572 2.2u_6.3V_Y 5V_06
C592 0.1u_16V_Y 5V_04
CLOSE TO SO-DIMM
MVR EF_CA_DIMMA_R
R443 1K_1%_04
1.5V
R 440 C594
1K_1%_04 0.1u_10V_X5R_04
D03 modify footprint 08->06
2,4,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,33,34,35,36,37,38,41,45,48
VTT_MEM
C328 C 324 C323 C334 C333
10u_6.3V_X5R _06 1u_6.3V_X5R _04 1u_6.3V_X5R_04
1u_6.3V_X5R_04 1u_6.3V_X5R_04
Schematic Diagrams
JDIMM3B
1.5V
75 44
VD D1 VSS16
76 48
VD D2 VSS17
81 49
VD D3 VSS18
82 54
VD D4 VSS19
87 55
VD D5 VSS20
88 60
VD D6 VSS21
93 61
VD D7 VSS22
94 65
VD D8 VSS23
99 66
VD D9 VSS24
100 71
VD D10 VSS25
105 72
VD D11 VSS26
106 127
VD D12 VSS27
111 128
VD D13 VSS28
112 133
VD D14 VSS29
117 134
VD D15 VSS30
118 138
Sheet 10 of 61
VD D16 VSS31
123 139
VD D17 VSS32
124 144
VD D18 VSS33
145
VSS34
199 150 DDRIII CHA SO-
VD DSPD VSS35
151
VSS36
77 155
NC1 VSS37
122 156
NC2 VSS38
125 161
NCTEST VSS39
162
VSS40
198 167
EVENT# VSS41
30 168
RESET# VSS42
172
VSS43
173
VSS44
1 178
VR EF_DQ VSS45
126 179
VR EF_CA VSS46
184
VSS47
185
VSS48
2 189
VSS1 VSS49
3 190
VSS2 VSS50
8 195
VSS3 VSS51
9 196
VSS4 VSS52
13
VSS5
14
VSS6
19
VSS7
20 VTT_MEM
VSS8
25
VSS9
26 203
VSS10 VTT1
31 204
VSS11 VTT2
32
VSS12
37 GN D1
VSS13 G1
38 GN D2
VSS14 G2
43
VSS15
DDR SK-20401-TR5B
MVREF_CA_DIMMA_R 11
11,12,13,43 VTT_MEM
4,7,11,12,13,27,31,41,43 1.5V
3.3VS
DDRIII CHA SO-DIMM_0 B - 11
DIMM _0