Processor 2/7 - Clevo P170EM Service Manual

Processor 2/7

Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
If PROCHOT# is not used,
then it must be terminated
with a 56-£[ +-5% pull-up
resistor to 1.05VS_VTT .
25,35 H_PECI
45 H_PROCHOT#
25 H_THRMTRIP#
22 H_PM_SY NC
25 H_CPUPWRGD
Buffered reset to CPU
3.3VS
R97
10K_04
2,14,24 PLT_RST#
5 G
6
D
R511 2 G Q37A
S MTDN7002ZHS6R
100K_04 1
C60
68P_50V_NPO_04
G
35 H_PROCHOT#_EC
R34
100K_04
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U32B
C26
PROC_SELET
25 H_SNB_IVB#
PROC_SELECT#
SKTOCC# AN34
SKTOCC#
AL33
H_CATERR#
CATERR#
R50 *10mil_short AN33
PECI
H_PROCHOT#_D AL32
R52 56_1%_04
PROCHOT#
R51 *10mil_short AN32
THERMTRIP#
AM34
R302 *10mil_short
PM_SY NC
H_CPUPWRGD_R AP33
R41 *10mil_short
UNCOREPWRGOOD
PMSYS_PWRGD_BUF VDDPWRGOOD_R V8
R521 130_1%_04
SM_DRAMPWROK
1.05VS_VTT BUF_CPU_RST# AR33
RESET#
R39
3 75_04
D
Iv y Bridge_rPGA_2DPC_Rev 0p61
R40 43_1%_04 BUF_CPU_RST#
S Q37B
4 MTDN7002ZHS6R
S3 circuit:- DRAM PWR GOOD logic
R38 *1.5K_1%_04
3.3V
R48
*750_1%_04
22 PM_DRAM_PWRGD
H_PROCHOT#
22,44 1.8VS_PWRGD
Q6
C82
MTN7002ZHS3
47P_50V_NPO_04
41,42,43,44
CAD Note: Capacitor need to be placed
close to buffer output pin
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A28
CLK_EXP_P 21
BCLK A27
CLK_EXP_N 21
BCLK#
A16
CLK_DP_P 21
DPLL_REF_CLK
A15
CLK_DP_N 21
DPLL_REF_CLK#
R8 CPUDRAMRST#
SM_DRAMRST#
AK1 SM_RCOMP_0
SM_RCOMP[0]
A5 SM_RCOMP_1
SM_RCOMP[1]
A4 SM_RCOMP_2
SM_RCOMP[2]
AP29 XDP_PRDY #
PRDY #
AP27 XDP_PREQ#
PREQ#
AR26
XDP_TCLK
TCK AR27
XDP_TMS
TMS
AP30
XDP_TRST#
TRST#
AR28 XDP_TDI_R
TDI
AP26 XDP_TDO_R
TDO
AL35
XDP_DBR_R
DBR#
AT28
BPM#[0]
AR29
BPM#[1]
AR30
BPM#[2]
AT30
BPM#[3]
AP32
BPM#[4]
AR31
BPM#[5]
AT31
S3 circuit:- DRAM_RST# to memory
BPM#[6]
AR32
BPM#[7]
should be high during S3
3.3V
CPUDRAMRST#
C306
R196 R199
1.5VS_CPU
4.99K_1%_04
R322
200_1%_04
1
4 PMSY S_PWRGD_BUF
2
U18
*MC74VHC1G08DFT1G R325
*39_04
3.3VS 2,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,33,34,35,36,37,38,41,45,48
3.3V 3,7,15,20,21,22,24,25,26,27,30,31,33,37,38,41,43,44
1.5V 7,10,11,12,13,27,31,41,43
R193 0_04
1.5VS_CPU 7,41
Q13
1.05VS_VTT 3,6,25,26,27,44,45,48
G
SUSB
*MTN7002ZHS3
Schematic Diagrams
PU/PD for JTAG signals
1.05VS_VTT
XDP_TMS R82 51_04
XDP_TDI_R R76 51_04
XDP_PREQ#
R84 *51_04
XDP_TDO_R
R308 51_04
XDP_TCLK
R309 51_04
XDP_TRST# R67 51_04
3.3VS
XDP_DBR_R 1K_04 R301
DDR3 Compensation Signals
SM_RCOMP_0 R409 140_1%_04
SM_RCOMP_1 R333 25.5_1%_04
SM_RCOMP_2
R334 200_1%_04
Processor Pullups/Pull downs
1.05VS_VTT
H_PROCHOT#
62_04 R42
H_CPUPWRGD_R 10K_1%_04 R49
P150HM_D04A C568 0.1u_16V_Y 5V_04
TRACE WIDTH 10MIL, LENGTH <500MILS
1.5V
R329
1K_04
R327 *0_04
BSS138 ( VGS 1.5V )
Q24
MTN7002ZHS3
S D
R331
R328 1K_04
DDR3_DRAMRST# 10,11,12,13
DRAMRST_CNTRL 7,21
C494
0.047u_10V_X7R_04
Sheet 4 of 61
Processor 2/7
Processor 2/7 B - 5