Ddr4 So-Dimm_0 - Clevo W517GU Service Manual

DDR4 SO-DIMM_0

5
[2] M_A_CKP0
[2] M_A_CKN0
[2] M_A_CKP1
[2] M_A_CKN1
[2] M_A_CKE0
[2] M_A_CKE1
[2] M_A_CS0_N
[2] M_A_CS1_N
[2] M_A_ODT0
D
[2] M_A_ODT1
[2] M_A_BG0
[2] M_A_BG1
[2] M_A_BA0
[2] M_A_BA1
[2] M_A_MA0
[2] M_A_MA1
[2] M_A_MA2
[2] M_A_MA3
[2] M_A_MA4
[2] M_A_MA5
[2] M_A_MA6
[2] M_A_MA7
[2] M_A_MA8
[2] M_A_MA9
[2] M_A_MA10
[2] M_A_MA11
[2] M_A_MA12
[2] M_A_MA13
[2] M_A_MA14
[2] M_A_MA15
1.2V
[2] M_A_MA16
[2] M_A_ACT_N
M_A_PARITY
R224
M_A_ALERT_N
1k_1%_04
R226
M_A_EVENT_N
C M_A_RESET_N_R
[2] M_A_RESET_N
+DIMM0_VREF_CA_R_1
0_04
[11] SMB_DAT_DDR
[11] SMB_CLK_DDR
1.2V
B
TP_DDR0_NC_CS1A
TP_DDR0_NC_CS0B
VTT_MEM
2.5V
C170 C174 C176 C366
10u_6.3V_X5R_06 1u_6.3V_X5R_04 1u_6.3V_X5R_04 10u_6.3V_X5R_06
1.2V
C352 C161 C162 C179 C181
+
22u_6.3V_X5R_06 22u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06
A
*330uF_2.5V_12m_6.6*6.6*4.2
1.2V
C164 C165 C166 C163 C180
1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04
5
4 3
JDIMM1A
137 8
M_A_DQ1 [2]
CK0_T DQ0
139 7
CK0_C DQ1 M_A_DQ0 [2]
138 20
M_A_DQ5 [2]
CK1_T DQ2
140 21
CK1_C DQ3 M_A_DQ7 [2]
4
M_A_DQ2 [2]
DQ4
109 3
CKE0 DQ5 M_A_DQ3 [2]
110 16
CKE1 DQ6 M_A_DQ6 [2]
17
DQ7 M_A_DQ4 [2]
149 28
BOT
S0* DQ8 M_A_DQ24 [2]
157 29
S1* DQ9 M_A_DQ29 [2]
41
DQ10 M_A_DQ28 [2]
155 42
M_A_DQ26 [2]
ODT0 DQ11
161 24
ODT1 DQ12 M_A_DQ25 [2]
25
M_A_DQ30 [2]
DQ13
115 38
BG0 DQ14 M_A_DQ31 [2]
113 37
M_A_DQ27 [2]
BG1 DQ15
150 50
BA0 DQ16 M_A_DQ19 [2]
145 49
M_A_DQ18 [2]
BA1 DQ17
62
DQ18 M_A_DQ23 [2]
144 63
M_A_DQ22 [2]
A0 DQ19
133 46
A1 DQ20 M_A_DQ17 [2]
132 45
SO-DIMM A
M_A_DQ16 [2]
A2 DQ21
131 58
A3 DQ22 M_A_DQ21 [2]
128 59
M_A_DQ20 [2]
A4 DQ23
126 70
A5 DQ24 M_A_DQ8 [2]
127 71
A6 DQ25 M_A_DQ9 [2]
122 83
A7 DQ26 M_A_DQ12 [2]
125 84
W>  >K^ dK ^K/DD
M_A_DQ13 [2]
A8 DQ27
121 66
A9 DQ28 M_A_DQ10 [2]
146 67
A10_AP DQ29 M_A_DQ15 [2]
120 79
M_A_EVENT_N
A11 DQ30 M_A_DQ11 [2]
119 80
A12 DQ31 M_A_DQ14 [2]
158 174 M_A_ALERT_N
A13 DQ32 M_A_DQ37 [2]
151 173
A14_WE* DQ33 M_A_DQ38 [2]
156 187 M_A_PARITY
M_A_DQ32 [2]
A15_CAS* DQ34
152 186
A16_RAS* DQ35 M_A_DQ34 [2]
170
M_A_DQ36 [2]
DQ36
169
DQ37 M_A_DQ39 [2]
114 183
M_A_DQ35 [2]
ACT* DQ38
182
DQ39 M_A_DQ33 [2]
143 195
M_A_DQ44 [2]
PARITY DQ40
116 194
ALERT* DQ41 M_A_DQ45 [2]
134 207
M_A_DQ42 [2]
EVENT* DQ42
108 208
RESET* DQ43 M_A_DQ43 [2]
191
M_A_DQ47 [2]
DQ44
164 190
VREFCA DQ45 M_A_DQ46 [2]
203
M_A_DQ41 [2]
DQ46
254 204
+DIMM0_VREF_CA_R_1
SDA DQ47 M_A_DQ40 [2]
253 216
M_A_DQ53 [2]
SCL DQ48
215
DQ49 M_A_DQ54 [2]
166 228
SA2 DQ50 M_A_DQ50 [2]
260 229
SA1 DQ51 M_A_DQ48 [2]
256 211
SA0 DQ52 M_A_DQ55 [2]
212
DQ53 M_A_DQ51 [2]
224
DQ54 M_A_DQ49 [2]
225
DQ55 M_A_DQ52 [2]
92 237
CB0_NC DQ56 M_A_DQ60 [2]
91 236
M_A_DQ62 [2]
CB1_NC DQ57
101 249
CB2_NC DQ58 M_A_DQ59 [2]
105 250
M_A_DQ58 [2]
CB3_NC DQ59
88 232
CB4_NC DQ60 M_A_DQ56 [2]
87 233
M_A_DQ61 [2]
CB5_NC DQ61
100 245
CB6_NC DQ62 M_A_DQ63 [2]
104 246
M_A_DQ57 [2]
CB7_NC DQ63
12 13
M_A_DQSP0 [2]
DM0*/DBI0* DQS0_T
33 34
DM1*/DBI1* DQS1_T M_A_DQSP3 [2]
54 55
M_A_DQSP2 [2]
DM2*/DBI2* DQS2_T
75 76
DM3*/DBI3* DQS3_T M_A_DQSP1 [2]
178 179
M_A_DQSP4 [2]
DM4*/DBI4* DQS4_T
199 200
DM5*/DBI5* DQS5_T M_A_DQSP5 [2]
220 221
M_A_DQSP6 [2]
DM6*/DBI6* DQS6_T
241 242
DM7*/DBI7* DQS7_T M_A_DQSP7 [2]
96 97
DM8*/DBI8* DQS8_T
11
DQS0_C M_A_DQSN0 [2]
32
DQS1_C M_A_DQSN3 [2]
53
DQS2_C M_A_DQSN2 [2]
74
M_A_DQSN1 [2]
DQS3_C
177
DQS4_C M_A_DQSN4 [2]
198
M_A_DQSN5 [2]
DQS5_C
219
DQS6_C M_A_DQSN6 [2]
1.2V
240
M_A_DQSN7 [2]
DQS7_C
95
DQS8_C
162
S2*/C0
165
S3*/C1
D4AS0-26001-1P40 R231
3.65K_1%_04
C367
1u_6.3V_X5R_04
R228
3.65K_1%_04
C183 C185 C159 C160
10u_6.3V_X5R_06 10u_6.3V_X5R_06 22u_6.3V_X5R_06 22u_6.3V_X5R_06
D02, 10u 22u ripple
C182 C184 C186
1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04
4 3
2
1.2V
JDIMM1B
163 258
VDD19 VTT
160
VDD18
159
VDD17
154 259
VDD16 VPP2
153 257
VDD15 VPP1
148
VDD14
147
VDD13
142
VDD12
141
VDD11
136 255
JDIMM1 = CHA DIMM0 000
VDD10 VDDSPD
135
VDD9
130
VDD8
129
VDD7
Modify,7/10 Max 124
VDD6
123
VDD5
118
VDD4
117
VDD3
112
VDD2
111
VDD1
GND1
MT1
GND2
MT2
251 252
VSS VSS
247 248
VSS VSS
243 244
1.2V
VSS VSS
239 238
VSS VSS
235 234
VSS VSS
231 230
240_1%_04 R227
VSS VSS
227 226
VSS VSS
R230 223 222
240_1%_04
VSS VSS
217 218
VSS VSS
R206
240_1%_04 213 214
VSS VSS
209 210
VSS VSS
205 206
VSS VSS
201 202
VSS VSS
197 196
VSS VSS
193 192
VSS VSS
189 188
VSS VSS
185 184
VSS VSS
181 180
VSS VSS
175 176
VSS VSS
171 172
W>  d,  W >K^ dK ^K/DD VSS VSS
167 168
VSS VSS
107 106
VSS VSS
103 102
VSS VSS
99 98
VSS VSS
93 94
VSS VSS
89 90
C178 VSS VSS
85 86
VSS VSS
81 82
*0.1u_16V_X7R_04 VSS VSS
77 78
VSS VSS
73 72
VSS VSS
69 68
VSS VSS
65 64
VSS VSS
61 60
VSS VSS
57 56
VSS VSS
51 52
VSS VSS
47 48
VSS VSS
43 44
VSS VSS
39 40
VSS VSS
35 36
VSS VSS
31 30
VSS VSS
27 26
VSS VSS
23 22
VSS VSS
19 18
VSS VSS
15 14
VSS VSS
9 10
VSS VSS
5 6
VSS VSS
1 2
VSS VSS
D4AS0-26001-1P40
+DIMM1_VREF_CA_RC
R229
+DIMM0_VREF_CA_R_1 +DIMM0_VREF_CA
M0_VREF_CA
2_1%_04 R222 0_04
C177 C175
*0.1u_16V_X7R_04 0.022u_16V_X7R_04
R223
24.9_1%_04
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
Title Title Title
[11,14,15,16,17,18,20,21,22,23,24,28] 3.3VS
[12] DDR4 SO-DIMM_0 [12] DDR4 SO-DIMM_0 [12] DDR4 SO-DIMM_0
[9,26] 1.2V
[26] VTT_MEM
Size Size Size Document Number Document Number Document Number
[26] 2.5V
Custom Custom Custom SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
Date: Date: Date: Tuesday, January 30, 2018 Tuesday, January 30, 2018 Tuesday, January 30, 2018
2
Schematic Diagrams
1
VTT_MEM
2.5V
3.3VS
C371
C370 D
0.1u_16V_X7R_04
2.2u_6.3V_X5R_04
W>  >K^ dK W/E
Sheet 12 of 31
DDR4 SO-DIMM_0
C
B
[2]
A
Rev Rev Rev
6-71-W51G0-D02 6-71-W51G0-D02 6-71-W51G0-D02
3.0 3.0 3.0
Sheet Sheet Sheet 12 12 12 of of of 35 35 35
1
DDR4 SO-DIMM_0 B - 13