National Instruments Data Acquisition Device E Series User Manual page 179

Appendix A Device-Specific Information
NI 6030E/6031E/6032E/6033E Dither
NI 6030E/6031E/6032E/6033E Block Diagrams
Voltage
REF
(8)*
Analog
Mux Mode
Muxes
(8)*
Calibration
Mux
2
Trigger Level
DACs
Trigger
PFI / Trigger
Timing
Digital I/O (8)
DAC0
DAC1
E Series User Manual
You cannot disable dither on the NI 6030E/6031E/6032E/6033E. The ADC
resolution is so fine that the ADC and the PGIA inherently produce almost
0.5 LSB of noise. This configuration is equivalent to having a dither
rms
circuit that is always enabled.
Figure A-40 shows a block diagram of the NI 6030E/6031E.
Calibration
DACs
3
+
Programmable
Selection
Gain
Switches
Amplifier
–
Configuration
Memory
Analog
Trigger
Circuitry
Trigger
Counter/
Timing I/O
Digital I/O
DAC
FIFO
Calibration
4
DACs
REF
Buffer
2
12-Bit
Sampling
ADC
A/D
FIFO
Converter
AI Control
IRQ
DMA
DMA/
Analog Input
Interrupt
Timing/Control
Request
Bus
DAQ - STC
Interface
Analog Output
RTSI Bus
Timing/Control
Interface
AO Control
Data (16) Data (16)
Figure A-40. NI 6030E/6031E Block Diagram
A-44
Control
PCI
Generic
Bus
MITE
Bus
Interface
Interface
Address/Data
EEPROM
Analog
EEPROM DMA
Input
Control Interface
Control
DAQ-STC
MIO
Bus
Interface
Interface
I/O
Analog
Bus
Output
Control Interface
RTSI
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