Figure 3-26. Rx/ Tx Ssi Configuration - Motorola APX 1000 Detailed Service Manual

Hide thumbs Also See for APX 1000:

Table of Contents

3.2.4.7 Double Data Rate (DDR) Memory (U6301)

The 32MB DDR Synchronous DRAM IC is interfaced to the OMAP using 13 address bits and a 16bit

data bus. The DDR IC is driven by a complementary clock signal originating from the OMAP IC. The

DDR clock is initialized to 96 MHz by the OMAP boot code. Additional control signals are also

dedicated for the DRAM interface

3.2.4.8 Peripheral Devices

The OMAP processor is equipped with multiple buses and interfaces that are configured for

peripheral interconnection.

3.2.4.8.1 Receive and Transmit SSI

These two interfaces are dedicated for communicating with the RF deck digital interface, carrying

receive and transmit base band signals. The OMAP processor generates the clock and FSYNC

signals for the receive SSI interface. The RF deck generates these signals for the transmit SSI

3.2.4.8.2 Audio SSI

OMAP's McBSP1 interface is configured as a SSI interface dedicated to carry transmit and receive

audio data to peripheral devices. The peripherals connected to this bus include MAKO, Audio

CODEC, MACE and CPLD. The bus also connects to the keypad board. MAKO generates the clock

and frame sync signals for this bus.

Figure 3-26. RX/ TX SSI Configuration

Theory of Operation

CONTROLLER SECTION

: Controller

Show Quick Links

Table of Contents

Apx 2000 Apx 4000li Apx 4000