Figure 8-18. Memory Interface Circuit (84012320001) - Motorola APX 1000 Detailed Service Manual

8-46
DDR INTERFACE
U6302 OMAP1710
D9 DDR_CLKX_1
SDCLKX
C9 DDR_CLK_1
SDCLK
H12 DDR_CLKE
SDCLK_EN
H8 DDR_WE
NSWE
DDR_BANK0
B3
SBANK_0
C3 DDR_BANK1
SBANK_1
0 D6 H7 DDR_RAS
SDATA_0 CONTROL NSRAS
1 C6 B4 DDR_CAS
SDATA_1 NSCAS
2 C5 G8 DDR_CS
SDATA_2
CS_SDRAM
3 D7 D10 DDR_UDM
SDATA_3
NSDQMU
4 D5 C8 DDR_LDM
SDATA_4 NSDQML
5 C7 C14 DDR_DQSH
SDATA_5 DSQ_H
C4 D4 DDR_DQSL
6
SDATA_6 DSQ_L
7 D8 A2 0
SDATA_7 SADD_0
8 C10 B2 1
SDATA_8 DATA SADD_1
9 D14 B6 2
SDATA_9 SADD_2
10 D11 A1 3
SDATA_10 SADD_3
11 C13 G10 4
SDATA_11
SADD_4
12 C11 B9 5
SDATA_12
SADD_5
13 D13 G12 6
SDATA_13 SADD_6
14 D12 G11
7
SDATA_14 ADDRESS SADD_7
C12 G9
15 8
SDATA_15 SADD_8
B12 9
SADD_9
B8 10
SADD_10
H10 11
SADD_11
H9 12
SADD_12
H11 13
SADD_13
DDR_ADDR<13..0>
DDR_DATA<17..0>
MMC INTERFACE
F2_TIMER_OUT
U6302
V11
MMC1_CLK
M15
OMAP1710
MMC1_CLKIN
P11
MMC1_CMD
P19
MMC1_CMDDIR
P20
MMC1_DATDIR0
P18
OPTION CARD INTF MMC1_DATDIR1
M14
MMC1_DATDIR2
R18
MMC1_DATDIR3
R11
MMC1_DAT0
V10
MMC1_DAT1
W10
MMC1_DAT2
W11
MMC1_DAT3
Y10
MMC2_CLK
Y8
MMC2_CMD
V9
MMC2_CMDDIR
V5
MMC2_DATDIR0
MEMORY CARD INTF
W19
MMC2_DATDIR1
W8
MMC2_DAT0
V8
MMC2_DAT1
W15
MMC2_DAT2
R10
MMC2_DAT3

Figure 8-18. Memory Interface Circuit (84012320001)

V_EXT_1.85
TP6307
R6301
10K TEST_POINT
DNP
TP6308
TEST_POINT
DNP U6301
MT46H16M16LF
G2
CLK
G3
CLK*
G1
0
EN_CLKE
1
2 0 DDR_WE G7
WE
3 4 DDR_CAS G8
CAS
4 3 DDR_RAS G9
RAS
5 DDR_CRTL<6..0> 5 DDR_CS H7
EN_CS
1 DDR_BANK0 H8
BA0
2 H9
BA1
J8
0 A0
1 J9
A1
2 DDR_ADDR<2> K7
A2
3 DDR_ADDR<3> K8
A3
4 DDR_ADDR<4> K2
A4
5 DDR_ADDR<5> K3
A5
6 DDR_ADDR<6> J1
A6
7 DDR_ADDR<7> J2
A7
DDR_ADDR<8> J3
8 A8
DDR_ADDR<9> H1
9 A9
10 DDR_ADDR<10> J7
A10_AP
11 DDR_ADDR<11> H2
A11
12 DDR_ADDR<12> H3
A12
DDR_UDM F2
UDM
DDR_LDM F8
LDM
13
R6305
0
RSW_A
OUT
DNP
TEST_POINT
1
TP6301
AVR_STATUS_1.8V
OUT
R6307
0 RSW_B
OUT
R63050
0
RSW_INT
OUT
Schematics, Boards Overlays, and Parts Lists: Transceiver (RF) Boards: VHF (84012320001 / PC000352A01)
1
TP6304 DNP
TEST_POINT
TP6303
1
TEST_POINT DNP
E2 DDR_DQSH
UDQS
E8 DDR_DQSL
LDQS
A8 0
DQ0 DDR_DATA<0>
B7 1
DQ1
DDR_DATA<1>
B8 2
DQ2
DDR_DATA<2>
C7 3
DQ3
DDR_DATA<3>
C8 4
DQ4
DDR_DATA<4>
D7 5
DQ5
DDR_DATA<5>
D8 6
DQ6
DDR_DATA<6>
E7 7
DQ7
DDR_DATA<7>
E3
8
DQ8 DDR_DATA<8>
D2 9
DQ9 DDR_DATA<9>
D3 10
DQ10
DDR_DATA<10>
C2 11
DQ11
DDR_DATA<11>
C3 12
DQ12
DDR_DATA<12>
B2 13
DQ13
DDR_DATA<13>
B3 14 PA_SHTDN
DQ14
DDR_DATA<14>
A2 15
DQ15
DDR_DATA<15>
F3
PA_SHTDN
NC1 NC
F7
NC2
FLASH INTERFACE
R6492
1.8K
TP6305 DNP
0 1
TEST_POINT
U6302
8 1
TP6306 OMAP1710
DNP
TEST_POINT
L4
NF_ADV
M7
NFCS_0
M3
NFCS_1
M4
NFCS_2
N8
NFCS_3
U4
NFOE
CONTROL
W1
NFRP
W2
NFWE
V4
NFWP
0 N4 N3
FDATA_0 FCLK
1 N2 V2
FDATA_1 FRDY
2 N7 J8
FDATA_2
FADD_1
3 P2 D3
FDATA_3
FADD_2
4 P4 C1
FDATA_4 FADD_3
P7 E4
5
FDATA_5 FADD_4
6 R2 D2
FDATA_6 FADD_5
7 R3 F4
FDATA_7 FADD_6
8 R4 E3
FDATA_8 DATA FADD_7
9 T2 J7
FDATA_9 FADD_8
10 T3 F3
FDATA_10 FADD_9
11 P8 G4
FDATA_11
FADD_10
12 U1 G3
FDATA_12
FADD_11
13 U3 G2
FDATA_13 FADD_12
T4 K8
14
FDATA_14 ADDRESS FADD_13
15 V3 H4
FDATA_15 FADD_14
H3
FADD_15
K7
FADD_16
J2
FADD_17
J4
FADD_18
J3
FADD_19
F2
FADD_20
L8
FADD_21
K4
FADD_22
K3
FADD_23
L7
FADD_24
E1
FADD_25
FLASH_DATA<15..0>
CHANGES MADE
ADDED PA_SHTDN TO PORT M7 & R6492
V_EXT_1.85
V_EXT_1.85
R6316
10K
FLASH_CTRL<8..0>
R6304
0
FLASH_RDY V_FLASH
7
V_EXT_1.85
R6306
10K
R6314
33
6 R6310
33
0
1 R6311 33 E6
CLK
B4
CE
WAIT
2 FLASH_OE_A F8
OE
8 4 R6313 G8
33 WE DQ0
TP6302 1 3 D4
RST DQ1
TEST_POINT
DNP 1 C6
WP DQ2
F6
R6312 33 2 0 ADV DQ3
3 DQ4
4
DQ5
1 A1
A1 DQ6
6 2 B1
A2 DQ7
7 3 C1
A3
1 4 D1
A4 DQ8
2 5 D2
A5 DQ9
3 6 A2
A6 DQ10
C2
4 7 A7 DQ11
A3
5 8 A8 DQ12
6 9 B3
A9 DQ13
7 10 C3
A10 DQ14
8 11 D3
A11 DQ15
9 12 C4
A12
10 13 A5
A13
11 14 B5
A14 RFU1
12 15 C5
A15 RFU2
D7
13 16 A16 RFU3
14 17 D8 A17 RFU4
15 18 A7
A18
16 19 B7
A19
17 20 C7
A20
18 21 C8
A21
19 22 A8
A22
20 23 G1
A23
21 24 H8
A24
B6
22 25 A25_512M
23 B8
A26_1G
NC
24
25
FLASH_ADDR<25..1>
C6308 C6309 C6310 C6311
0.1UF 0.1UF 0.1UF 0.1UF
U6304
F7
0
F2
1
E2
2
G3
3
E4
4
E5
5
G5
6
G6
7
H7
8
E1
9
E3
10
F3
11
F4
12
F5
13
H5
14
G7
15
E7
E8 NC
F1 NC
G2 NC
H1
NC