Twi Master Mode Control Register (Twi_Master_Ctl) - Analog Devices ADSP-BF59x Blackfin Hardware Reference Manual

This bit self clears if slave mode is disabled (
[0] At the time of addressing, the address was not determined to be
a general call.
[1] At the time of addressing, the address was determined to be a
general call.
• Slave transfer direction (
This bit self clears if slave mode is disabled (
[0] At the time of addressing, the transfer direction was determined
to be slave receive.
[1] At the time of addressing, the transfer direction was determined
to be slave transmit.
TWI Master Mode Control Register
(TWI_MASTER_CTL)
The
TWI_MASTER_CTL
mode operation. Bits in this register do not affect slave mode operation
and should not be modified to control slave mode functionality.

TWI Master Mode Control Register (TWI_MASTER_CTL)

15 14 13 12 11 10
0 0
SCLOVR (Serial
Clock Override)
SDAOVR (Serial
Data Override)
DCNT[7:0] (Data
Transfer Count)
Figure 12-19. TWI Master Mode Control Register
ADSP-BF59x Blackfin Processor Hardware Reference
SDIR
register controls the logic associated with master
9 8 7 6
0 0 0 0 0 0 0 0
Two Wire Interface Controller
SEN
)
SEN
5 4 3 2 1 0
0 0 0 0 0 0 Reset = 0x0000
MEN (Master Mode Enable)
MDIR (Master Transfer
Direction)
FAST (Fast Mode)
STOP (Issue Stop
Condition)
RSTART (Repeat Start)
= 0).
= 0).
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