Dma Registers; Dma Channel Registers - Analog Devices ADSP-BF59x Blackfin Hardware Reference Manual

DMA Registers

"Handshaked Memory DMA Operation" on page
descriptor chains or rings this way, the whole DMA transaction can be
broken into pieces that are individually triggered by software.

Source and destination channels of a MDMA may differ in descrip-
tor structure. However, the total work count must match when the
DMA stops. Whenever a MDMA is stopped, destination and
source channels should both provide the same
exactly the same number of words. Accordingly, both channels
need to be started afterward.
Software-triggered descriptor fetches are illustrated in
page 5-96. MDMA channels can be paused by software at any time by
writing a 0 to the
disables the self-generated DMA requests, whether or not the HMDMA is
enabled.
DMA Registers
DMA registers fall into three categories:

• DMA channel registers

• Handshaked MDMA registers
• Global DMA traffic control registers
DMA Channel Registers
A processor features up to twelve peripheral DMA channels and two chan-
nel pairs for memory DMA. All channels have an identical set of registers
as summarized in
Table 5-6 lists the generic names of the DMA registers. For each register,
the table also shows the MMR offset, a brief description of the register,
5-62
bit field in the
DRQ
Table 5-6.
ADSP-BF59x Blackfin Processor Hardware Reference
5-36). By halting
FLOW
Listing 5-7 on
register. This simply
HMDMAx_CONTROL
= 0 mode after