Uart Controller Registers - Analog Devices ADSP-BF59x Blackfin Hardware Reference Manual

UART Controller Registers

UART Controller Registers
UART controller registers (0xFFC0 0400 – 0xFFC0 04FF) are listed in
Table A-18.
Table A-18. UART Controller Registers
Memory-Mapped
Address
0xFFC0 0400
0xFFC0 0400
0xFFC0 0400
0xFFC0 0404
0xFFC0 0404
0xFFC0 0408
0xFFC0 040C
0xFFC0 0410
0xFFC0 0414
0xFFC0 041C
0xFFC0 0424
A-18
Register Name For individual bits, see this diagram:
UART_THR "UART Transmit Holding (UART_THR) Register" on
page 11-25
UART_RBR "UART Receive Buffer (UART_RBR) Register" on
page 11-26
UART_DLL "UART Divisor Latch (UART_DLL and UART_DLH)
Registers" on page 11-29
UART_DLH "UART Divisor Latch (UART_DLL and UART_DLH)
Registers" on page 11-29
UART_IER "UART Interrupt Enable (UART_IER) Register" on
page 11-26
UART_IIR "UART Interrupt Identification (UART_IIR) Register" on
page 11-28
UART_LCR "UART Line Control (UART_LCR) Register" on
page 11-21
UART_MCR "UART Modem Control (UART_MCR) Register" on
page 11-23
UART_LSR "UART Line Status (UART_LSR) Register" on page 11-24
UART_SCR "UART Scratch (UART_SCR) Register" on page 11-30
UART_GCTL "UART Global Control (UART_GCTL) Register" on
page 11-31
ADSP-BF59x Blackfin Processor Hardware Reference