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IC BLOCK DIAGRAM~ERMINAL
FUNCTION (RADIO/GENERAL
SECTION)
~
I: Input o: OUtPUt
Pin
No.
5
6
7
8
9
10
11
12
13
14
15
16
/0
o
&ch
pen
J-ch
pen
I
I
o
0
0
0
0
0
I
I
Terminal
Name
DO
SYC
INO
IN1
LCTR
HCTR
Description
Output data
~Output terminal for serial data transferred
from the LC7219 to the controller.
~A total of 28 bits of internal shift register
data can be output in synchronization with
the CL.
Controller clock
Controller clock output terminal from which
400kHz (duty 66Yo) is output after power-on.
Input port
The contents of input ports INO, IN1 are
converted from parallel to serial and can
be output from output terminal DO.
output port
00 to
06
of serial
data
transferred
from
the
controller
are
latched
and
the
data
is
inverted
and
output
in parallel.
OUTO can output the time base for clock
(8Hz). (When TB=l)
OUT1 and 0UT2 provide complementary
output.
OUTO, 0UT3, 0UT4, 0UT5 and 0UT6
provide N-Ch open drain output (dielectric
withstand voltage 13V).
General-purpose counter frequency/cycle
measurement signal input terminal
Set serial data input: SC to O to select LCTR.
At this time, if serial data input: SF is set to 1;
This terminal enters the frequency
measurement mode.
The input frequency is 15 to 500kHz
(70mVrms rein).
The signal is transmitted directly to the
general-purpose counter without being
transmitted via the internal 1/8 divider.
The measurement time is the same as in
HCTR,
If serial data input: SF is set to O;
This terminal enters the cycle
measurement mode.
The input frequency is 1Hz to 20kHz
(VlH=0.7VDDmin,
VIL=O.3VDDmax).
The measurement cycle can be selected
between 1 cycle and 2 cycles, When 2
cycles are selected, the input frequency
is 2Hz to 20kHz (GT=l/0:
2/1 cycle).
The measurement result output method is
the same as in HCTR.
General-purpose counter frequency
measurement signal input terminal
Set serial data input: SC to 1 to select HCTR
The input frequency is 10 to 60MHz.
(70mVrms rein).
The signal is transmitted to the general-
purpose counter (20-bit binary counter) via
the internal 1/8 divider. Hence, the value o
the general-purpose counter is 1/8 of the
actual frequency entered into the HCTR
terminal.
When HCTR is selected, this terminal
enters the frequency measurement mode,
in which the measurement time can be
selected between 30msec and 60msec
(GT=l /0: 30/60msec).
The measurement result can be output
from MSB of the general-purpose counter
throuah outDut terminal DO.
3ifl
1/0
Terminal
No.
Name
Description
17
0
0UT6
output port
00
to 06
of serial
data
transferred
from
the
controller
are
latched
and
the
data
is
inverted
and
output
in parallel.
OUTO can output the time base for clock
(8Hz). (When TB=l )
OUT1 and 0UT2 provide complementary
output.
OUTO, 0UT3, 0UT4, 0UT5 and 0UT6
provide N-Ch open drain output (dielectric
withstand voltage 13V).
18
I
AM IN
Local oscillation signal input
Serial data input: Set DV to O to select
AMIN.
Serial data input: When SP is set to 1
The input frequency is 2 to 40 MHz
(70mVrms rein).
The signal is transmitted to the swallow
counter without passing through the built-
in prescaler (1/2).
The set submultiple is 256 to 65,536 and
the actual submultiple is the same as the
set value.
c Serial data input: When SP is set to O
The input frequency is 0.5 to 10 MHz
(70mVrms rein).
The signal is transmitted directly to the
12-bit programmable divider.
The set submultiple is 4 to 4096 and the
actual submultiple is the same as the set
value.
19
I
FM IN
Local oscillation signal input
Serial data input: Set DV to 1 to select FM IN.
The input frequency is 10 to 130 MHz
(70mVrms rein).
The signal is transmitted to the swallow
counter through the built-in prescaler (1/2).
Though the set submultiple is 256 to
65536, the actual submultiple is twice the
set value because of the built-in prescaler
(1/2),
20
-
VDD
Power supply
Power supply terminal of the LC7219.
Supplies 4.5 to 6.5V when the PLL is
activated. The voltage can be reduced
down, to 3.5V when only the crystal
oscillation circuit is activated to provide
the controller clock and clock time base.
21
3-state
PD1
Charge pump output
22
3-state
PD2
Charge pump output terminals of the PLL.
If the frequency which is an N submultiple
of the local oscillation signal frequency is
higher than the reference frequency, a high
level is output from PD1 and PD2. If the
frequency is lower, a low level is output.
If they match, the terminals are placed in a
floating state.
23
-
CD
Chip enable
Terminal where the level is switched high
when serial data is input (Dl) to or output
(DO) from the LC7219.
24
0
Xout
Xtal OSC
Crystal oscillator connection (7.2MHz)
-58-
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