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IC502 (CXD2517Q)
I!@@
1: Input
0: output
Pin
1/0
Terminal
No.
Name
Description
1
I
FOK
Focus OK input terminal. Used for the SENE
output and servo auto sequencer.
2
0
MON
Spindle motor ON-OFF control output
3
0
MDP
Spindle motor servo control
4
0
MDS
Spindle motor servo control
5
0
LOCK
Samples GFS at 460Hz and outputs High
when GFS is High. Outputs Low when GFS
is Low eight consecutive
times,
6
I
TEST
Test terminal. Normally GND,
7
0
FILO
Filter output for master PLL
(slave=digital
PLL)
8
I
FILI
Filter input for master PLL
9
0
Pco
Charge pump output for master PLL
10
-
Vss
GND
11
-
AVSS
Analog GND
12
I
CLTV
VCO control voltage input for master
13
-
AVDD
Analog power supply (+5V)
14
I
RF
EFM signal input
15
I
BIAS
Constant current input for asymmetry circuit
16
I
ASYI
Asymmetry
comparator
voltage input
17
0
ASYO
EFM full-swing output (Low=VSS,
High=VDD)
18
I
ASYE
Low: asymmetry circuit off, High: asymmetry
circuit on
19
0
WDCK
D/A Interface. Word clock f=2Fs.
20
0
LRCK
D/A interface. LR clock f=Fs.
21
0
PCMD
D/A interface. Serial data (2's complement,
MSB first)
22
0
BCK
D/A interface. Blt clock.
23
0
GTOP
GTOP output
24
0
XUGF
XUGF output
25
0
XPCK
XPLCK output
26
-
VDO
Power supply (+5V)
27
0
GFS
GFS output
28
0
RFCK
RFCK output
29
0
C2P0
C2P0 output
30
0
XROF
XRAOF output
31
0
MNT3
MNT3 output
32
0
MNT1
MNT1 output
Pin
1/0
Terminal
No,
Name
Description
33
0
MNTO
MNTO output
34
I
XTAI
16.9344MHz
c~stal oscillation circuit input,
or 33.8688 MHz input.
35
0
XTAO
16.9344MHz
crystal oscillation circuit output
36
I
XTSL
Crystal select input terminal. Switched Low
when the crystal is 16.9344MHz.
Switched
High when the crystal is 33.8688MHz.
37
0
FSTT
Terminal 34, 35 2/3 frequency divider output
38
0
C4M
4.2336 MHz output
39
0
DOUT
Digital_Out
output terminal
40
0
EMPH
Outputs High when the disc played has
emphasis. Outputs Low when the disc has
no emphasis.
41
0
WFCK
WFCK output
42
–
Vss
GND
43
0
SCOR
Outputs High when either sub code sync SO
or S1 is detected.
44
0
SBSO
Serial output of sub P-W
45
I
EXCK
SBSO readout clock input
46
0
SQSO
SubQ 80-bit serial output
47
I
SQCK
SQSO readout clock input
48
I
MUTE
High: mute, Low: release
49
0
SENS
SENS output to the CPU.
50
I
XRST
System reset. Low for reset.
51
I
DATA
Serial data input from the CPU.
52
I
XLAT
Latch input from the CPU. Serial data is
latched at the falling edge.
53
I
CLOK
Serial data transfer clock input from the CPU
54
I
SEIN
SENS input from SSP
55
I
CNIN
Track jump count signal input
56
0
DATO
Serial data output to SSP
57
0
XLTO
Serial data latch output to SSP. Latched at
the falling edge.
58
-
VDD
Power supply (+5V)
59
0
CLKO
Serial data transfer clock output to SSP
60
I
SPOA
Microprocessor
extended interface (input A)
61
I
SPOB
Microprocessor
extended interface (input B)
62
I
SPOC
Microprocessor
extended interface (input C)
63
I
SPOD
Microprocessor
extended interface (input D)
64
0
XLON
Microprocessor
extended interface (output)
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