Yamaha CRX-E150 Service Manual page 21

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3 7 63 1515 0
Pin No.
Name
47
DSLF
48
PLLF
49
VCOF
50
AVDD2
51
AVSS2
52
EFM
53
PCK/
RESY
54
FLAG
55
CRC
56
XSEL
57
VSS
58
X1
59
X2
60
VDD
61
VCOF2
62
AVSS1
63
OUT1C
64
OUT1D
65
OUT2D
TE
L 13942296513
66
OUT2C
67
AVDD1
68
DEMPO
69
CK384
70
IOSEL
71
TEST
72
SBCK2
73
SUBC
74
SBCK
75
CLDCK
76
IPFLAG
77
DEMPI
/TEST2
78
SDATI
79
LRCKI
80
BCKI
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I/O
I/O
Loop filter terminal for DSL
I/O
Loop filter terminal for PLL
I/O
Loop filter terminal for VCO
I
Power supply for analog circuit (for AD of DSL, PLL, DA output blocks)
I
GND for analog circuit (for AD of DSL, PLL, DA output blocks)
O
EFM signal output
O
With command defaulted : PLL extract clock output PCK when IOSEL=H, frame re-synchronous signal RESY when IOSEL=L
These settings can be reversed by command (RESY when IOSEL=H).
O
Flag signal output
O
Sub-code CRC check result output (H : OK, L : NG)
I
L : Normal mode
H : • For internal master clock, VCO2 output clock for jitter adsorbing PLL is used instead of Xtal
oscillation output (X2).
• VCO2 is always fixed to oscillation mode regardless of VCO2 oscillation stop command or
resetting (/RST=L) and Xtal oscillation is stopped.
I
GND for oscillation circuit
I
Crystal oscillation circuit input terminal
O
Crystal oscillation circuit output terminal
I
Power supply for oscillation circuit
O
PLL loop filter terminal for jitter adsorption
O
GND for audio DAC
O
PEM output terminal 1C
O
PEM output terminal 1D
O
PEM output terminal 2D
O
PEM output terminal 2C
I
Power supply terminal for audio DAC
O
Deemphasis detect signal output
O
384fs clock output (At the CK384 pin, output does not stop while /RST=L.)
Xtal system when command is defaulted. Signal processing system when command is switched
I
Mode selecting terminal
I
Test mode setting terminal (Normal : H)
I
Sub-code data read clock input
O
Sub-code serial output (SBCK effective) when command is defaulted.
PACK data usable (SBCK2 effective) when command is switched
I
Clock input for sub-code serial output (with pull-up resistor)
O
Sub-code frame clock signal output when command is defaulted (fCLDCK=7.35kHz)
PACK synchronous signal when command is switched
O
Interpolation flag signal output (H : INTERPOLATION)
I
When IOSEL=H, L : NORMAL H : TEST2
Emphasis control in accordance with DEMP0
When IOSEL=L, external DEMP1 input terminal
For emphasis control, DEMP0, OR of DEMP1, DEMP1, forced OFF or forced ON is selected by command.
When command is defaulted, DEMP0 and OR of DEMP1
I
SRDATA input (effective only when IOSEL=L)
I
LRCK input (effective only when IOSEL=L) H : Lch data, L : Rch data
I
BCK input (effective only when IOSEL=L)
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2 9
8
Function
Q Q
3
6 7
1 3
1 5
co
.
CRX-E150
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
(+5)
(+5)
(GND)
(NC)
(NC)
(NC)
(NC)
(GND)
(+5)
(GND)
9 9
(NC)
(NC)
(+5)
(+5)
(NC)
(NC)
(GND)
(NC)
(NC)
(NC)
20

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