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Denon S-302 Service Manual page 66

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K4S641632 (IC103: 1U3808)
PIN FUNCTION DESCRIPTION
Pin
CLK
System clock
CS
Chip select
TE
L 13942296513
CKE
Clock enable
A
~ A
Address
0
11
BA
~ BA
Bank select address
0
1
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
L(U)DQM
Data input/output mask
DQ
~
Data input/output
0
15
V
/V
Power supply/ground
DD
SS
V
/V
Data output power/ground
DDQ
SSQ
No connection
N.C/RFU
/reserved for future use
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V
1
DD
DQ0
2
V
3
DDQ
DQ1
4
DQ2
5
V
6
SSQ
DQ3
7
DQ4
8
V
9
DDQ
DQ5
10
DQ6
11
V
12
SSQ
DQ7
13
V
14
DD
LDQM
15
WE
16
CAS
17
RAS
18
CS
19
BA0
20
BA1
21
A10/AP
22
A0
23
A1
24
A2
25
A3
26
V
27
DD
Name
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
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2 9
8
V
54
SS
53
DQ15
V
52
SSQ
DQ14
51
DQ13
50
V
49
DDQ
DQ12
48
DQ11
47
V
46
SSQ
DQ10
45
DQ9
44
V
43
DDQ
DQ8
42
V
41
SS
N.C/RFU
40
UDQM
39
CLK
38
37
CKE
N.C
36
A11
35
A9
34
A8
33
A7
32
A6
31
A5
30
A4
29
(400mil x 875mil)
V
28
SS
(0.8 mm Pin pitch)
Input Function
Q Q
3
6 7
1 3
1 5
~ RA
, Column address : CA
0
11
after the clock and masks the output.
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66
9 4
2 8
54Pin TSOP (II)
0 5
8
2 9
9 4
2 8
~ CA
0
7
m
S-302
9 9
9 9

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