Denon S-302 Service Manual page 49

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3 7 63 1515 0
Name
TSD0
SEL_PLL0
TSD1
SEL_PLL1
TSD2
TSD3
MCLK
TBCK
SEL_PLL3
SPDIF_OUT
SPDIF_IN
RSD
RWS
RBCK
TE
L 13942296513
CAMIN3
PIXIN3
XIN
XOUT
AVEE
AVSS
DMA[11:0]
DCAS#
DOE#
DSCK_EN
DWE#
DRAS#
DMBS0
DMBS1
DB[15:0] 77-82, 85-90, 93-96
DCS[1:0]#
DQM
DSCK
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Pin Numbers I/O Definition
O Audio transmit serial data output 0.
33
I Refer to the description and matrix for SEL_PLL2 pin 32.
O Audio transmit serial data output 1.
36
I Refer to the description and matrix for SEL_PLL2 pin 32.
37 O Audio transmit serial data output 2. This pin must be pulled down to VSS via a
4.7-k resistor for proper operation.
38 O Audio transmit serial data output 3.
39 I/O Audio master clock for audio DAC.
40 I/O Audio transmit bit clock. TBCK is an input during reset and subsequently is
programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).
I Clock source select. Strapped to VCC or ground via 4.7-k
during reset.
41
O S/PDIF output.
42 I S/PDIF input; (5V tolerant input).
45 I Audio receive serial data; (5V tolerant input).
46 I Audio receive frame sync; (5V tolerant input).
47 I Audio receive bit clock; (5V tolerant input).
I Camera YUV 3.
48
I CCIR656 input pixel 3.
49 I 27-MHz crystal input.
50 O 27-MHz crystal output.
51 P Analog power for PLL.
52 G Analog ground for PLL.
53-58, 61-66 O DRAM address bus.
69 O DRAM column address strobe.
O DRAM output enable.
70
O DRAM clock enable.
71 O DRAM write enable.
72 O DRAM row address strobe.
73 O DRAM bank select 0.
74 O DRAM bank select 1.
I/O DRAM data bus.
97,100 O DRAM chip select.
101 O Data input/output mask.
102 O Output clock to DRAM.
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8
SEL_PLL3 Clock Source
0 Crystal oscillator
1 DCLK input
Q Q
3 6 7 1 3
u163
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49
2 9 9 4 2 8
resistor; read only
1 5 0 5 8 2 9 9 4
m
co
S-302
9 9
2 8 9 9