Denon S-302 Service Manual page 65

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NT5DS16M16CS (IC202: 1U-3809)
Input/Output Functional Description
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L 13942296513
Symbol
CK, CK
CKE
CS
RAS, CAS, WE
DM
BA0, BA1
A0 - A12
DQ
DQS, LDQS, UDQS
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DDQ
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SSQ
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Type
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
Input on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self
Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn-
Input chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin.
Chip Select: All commands are masked when CS is registered high. CS provides for external
Input bank selection on systems with multiple banks. CS is considered part of the command code. The
standard pinout includes one CS pin.
Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
Input
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-
ing a Read, DM can be driven high, low, or floated.
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge
Input command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
Address Inputs: Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
Input
charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode
Register Set command.
Input/Output Data Input/Output: Data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
Input/Output in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-
DQ7; UDQS corresponds to the data on DQ8-DQ15
No Connect: No internal electrical connection is present.
Electrical connection is present. Should not be connected at second level of assembly.
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DQ Power Supply: 2.5V ± 0.2V for DDR333; 2.6V ± 0.1V for DDR400.
Supply
Supply DQ Ground
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Power Supply: 2.5V ± 0.2V for DDR333; 2.6V ± 0.1V for DDR400.
Supply
Supply Ground
Supply SSTL_2 reference voltage
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