Denon S-302 Service Manual page 62

QQ
3 7 63 1515 0
Pin No Port name
23 P84/INT2
24 P83/INT1
25 P82/INT0
26 P81/TA4IN
27 P80
28 P77
29 P76
30 P75/TA2IN
31 P74/TA2OUT
32 P73/CTS2/TA1IN
33 P72/CLK2
34 P71/RXD2
35 P70/TXD2
36 P67/TXD1
37 VCC1
38 P66/RXD1
39 VSS
40 P65/CLK1
41 P64/CTS1
42 P63/TXD0
43 P62/RXD0
44 P61/CLK0
45 P60/CTS0
46 P137
47 P136
48 P135
49 P134
50 P57
51 P56
52 P55/EPM
53 P54
TE
L 13942296513
54 P133
55 P132
56 P131
57 P130
58 P53
59 P52
60 P51
61 P50/CE
62 P127
63 P126
64 P125
65 P47
66 P46
67 P45
68 P44
69 P43
70 P42
71 P41
72 P40
73 P37
74 P36
75 P35
76 P34
77 P33
78 P32
79 P31
80 P124
81 P123
www
82 P122
83 P121
84 P120
85 VCC2
.
86 P30
87 VSS
88 P27
89 P26
http://www.xiaoyu163.com
Function I/O
_DIR_INT I
SUB_ACK I
N.C. O
N.C. O
PWB_CHK O
_DEC_RST O
_ENC2_RST O
N.C.
N.C.
N.C.
N.C. O
N.C. O
N.C. O
F_TXD2 O
VCC1 -
F_RXD2 O
VSS -
N.C. O
N.C. O
SUB_STXD O
SUB_SRXD I
SUB_CLK I
SUB_REQ O
CK_SEL O
HD/_SD O
HDMI_DEBUG_3 O
HDMI_DEBUG_6 O
_ENC1_RST O
V_DET I
F_EPM2 O
N.C. O
N.C. O
HDMI_SCL I/O
HDMI_SDA I/O
VD_SCL I/O
VD_SDA I/O
N.C. O
N.C. O
_F_CE2 O
P_SAVE O
N.C. O
N.C. O
N.C. O
N.C. O
FNVL_DA O
FNVL_CK O
FNVL_CE O
N.C. O
N.C. O
N.C. O
N.C. O
N.C. O
N.C. O
EXT_CK O
EXT_DA O
CODEC_MISO I
HDMI SENS I
VSEL_CS1 O
VSEL_CS2 O
CODEC_RST O
PRE_MUTE_SUB O
x ao u163
y
HP_MUTE_SUB O
VCC2 -
i
BE/_DIR O
VSS -
CODEC_CE O
TCK_AV O
http://www.xiaoyu163.com
2 9
8
DIR interrupt input
MAIN-SUB uCom communications control input terminal (ACK "L" return from main uCom)
OPEN
OPEN
PWB check
Reset for ADV7403
Reset for ADV7320-2
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
Data output for Flash rewriting /HDMI DEBUG 5 (DEBUG output for communication)
+3.3V
Data output for Flash rewriting /HDMI DEBUG 4 (DEBUG output for communication)
GND
OPEN
OPEN
Data output to of main uCom
Data input to of main uCom
Clock input from of main uCom
Communication Request to of main uCom
Video Encoder clock switching for ZONE2
VideoEncoder resolution switching(SD/SD or more)
HDMI DEBUG 3 (DEBUG output)
HDMI DEBUG 6 (DEBUG output)
Reset for ADV7320-1
CVBS video input detection
Port for Flash rewriting/HDMI DEBUG 2 (DEBUG output)
OPEN
Q Q
3 6 7 1 3 1 5
OPEN
VIDEO I2C clock (HDMI system)
VIDEO I2C data (HDMI system)
VIDEO I2C clock (Video processing system)
VIDEO I2C data (Video processing system)
OPEN
OPEN
Port for Flash rewriting/HDMI DEBUG 1 (DEBUG output)
COMPONENT CONVERT route DISABLE terminal
OPEN
OPEN
OPEN
OPEN
Function volume IC data output (RENESAS system data)
Function volume IC clock output (RENESAS system clock)
Function volume IC latch output (RENESAS system latch )
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
Video system (+5V system) expansion output port clock output
Video system (+5V system) expansion output port clock output
Data input from CODEC
HDMI IN signal presence detection input
Video selector PLD chip select
Video selector FPGA chip select
CODEC reset output
Mute output of volume output
co
MUTE output of head phone MUTE:H
+3.3V
.
Route of voice output (BE/external input) switching
GND
ODEC chip enabling
Main PLD JTAG
62
9 4 2 8
Explanation
0 5 8 2 9 9 4 2 8
m
S-302
9 9
9 9