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4-3 PLL CIRCUIT (RF UNIT)
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains a VCO (Q4, Q5, D4, D6). The oscil-
lated signal is amplified at the buffer-amplifiers (Q6, Q7) and
then applied to the PLL IC (IC1, pin 2).
The PLL IC contains the prescalers, programmable counter,
programmable divider, phase selector and etc. The entered
signal is divided at the prescaler and programmable counter
sections by the N-data ratio from the CPU. The divided sig-
nal is detected on phase at the phase detector using the ref-
erence frequency.
If the oscillated signal drifts, the phase of its frequency
changes from the reference frequency, causing a lock volt-
age changes to compensate for the drift in the oscillated fre-
quency.
A portion of the VCO signal is amplified at buffer-amplifiers
(Q6, Q8) and is then applied to the receive 1st mixer (Q14)
or transmit driver via the TX/RX switching diode (D7, D8).
The lock voltage is also used for the receiver tunable band-
pass filter to match the filter's center frequency to the
desired receive frequency. The lock voltage is amplified at
the buffer-amplifier (Q1) and then applied to the CPU (MAIN
unit; IC9, pin 93).
The amplified signal is controlled by the CPU (MAIN unit;
IC9), and is then applied to bandpass filters (D13–D18) as
"T1", "T2", "T3", "T4" signals via the D/A converter (IC2).
PLL CIRCUIT
Loop
filter
"2nd LO" signal (21.25 MHz)
to the FM IF IC (MAIN unit; IC1)
X1
21.25 MHz
"LVIN" signal to the CPU
Buffer
(MAIN unit; IC9)
Q1
VCO
Q4, Q5, D5, D6
Phase
8
detector
Programmable
17
divider
16
4-4 POWER SUPPLY CIRCUITS
VOLTAGE LINES
LINE
HV
The voltage from the attached battery pack.
The same voltage as the HV line (battery volt-
VCC
age) which is controlled by the power switch
([OFF/VOL] control).
Common 4V converted from the VCC line by the
4V regulator circuit (MAIN unit; Q8–Q10).
4V
The output voltage is applied to the D/A convert-
er (RF unit; IC2) and PLL IC (RF unit; IC1), etc.
Receive 4V converted from the 4V line by the R4
regulator circuit (MAIN unit; Q5).
R4V
The regulated voltage is applied to the MOD
MUTE circuit (RF unit; Q2, D2) and receiver cir-
cuit.
Transmit 4V converted from the 4V line by the T4
regulator circuit (MAIN unit; Q6).
T4V
The regulated voltage is applied to the transmit-
ter circuit.
Common 4V converted from the 4V line by the
S4V regulator circuit (MAIN unit; Q7).
S4V
The regulated voltage is applied to the optional
scrambler unit, limiter amplifier (MAIN unit; IC4),
etc.
Buffer
Q8
Buffer
Q6
Buffer
Q7
IC1 (PLL IC)
Programmable
2
Prescaler
counter
3
4
Shift register
5
4 - 3
DESCRIPTION
D8
to transmitter circuit
to 1st mixer circuit
D7
PLST
SCK
SO
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