Strobe Signal Output Registers; Strobe Output Registers - Point Grey Flea3 FL3-U3 Technical Reference Manual

Point Grey Flea3 USB 3.0 Technical Reference
4.3.4

Strobe Signal Output Registers

This section describes the control and inquiry registers for the Strobe Signal functionality.
4.3.4.1

Strobe Output Registers

Format:
Offset
STROBE_
48Ch OUTPUT_CSR_
INQ
Base + STROBE_CTRL_
0h INQ
Base +
STROBE_0_INQ
100h
Base +
STROBE_1_INQ
104h
Base +
STROBE_2_INQ
108h
Base +
STROBE_3_INQ
10Ch
Revised 9/27/2012
Copyright ©2011-2012 Point Grey Research Inc.
To calculate the base address for an offset CSR:
1. Query the offset inquiry register.
2. Multiple the value by 4. (The value is a 32-bit offset.)
3. Remove the 0xF prefix from the result. (i.e., F70000h becomes 70000h)
Name Field
Strobe_Output_
Quadlet_Offset
Strobe_0_Inq
Strobe_1_Inq
Strobe_2_Inq
Strobe_3_Inq
-
Presence_Inq
ReadOut_Inq
On_Off_Inq
Polarity_Inq
Min_Value
Max_Value
Same definition as Strobe_0_Inq
Same definition as Strobe_0_Inq
Same definition as Strobe_0_Inq
Bit
32-bit offset of the Strobe output signal CSRs from the base
[0-31]
address of initial register space
[0] Presence of strobe 0 signal
[1] Presence of strobe 1 signal
[2] Presence of strobe 2 signal
[3] Presence of strobe 3 signal
[4-31] Reserved
[0] Presence of this feature
[1-3] Reserved
[4] Ability to read the value of this feature
[5] Ability to switch feature ON and OFF
[6] Ability to change signal polarity
[7] Reserved
[8-19] Minimum value for this feature control
[20-31] Maximum value for this feature control
4 Input/Output Control
Description
47