Format_7_Resize_Inq: 1Ac8H; Inquiry Registers For Custom Video Mode Offset Addresses - Point Grey Flea3 FL3-U3 Technical Reference Manual

Point Grey Flea3 USB 3.0 Technical Reference
A.3.1

FORMAT_7_RESIZE_INQ: 1AC8h

This register reports all internal camera processes being used to generate images in the current video mode. For
example, users can read this register to determine if pixel binning and/or subsampling is being used to achieve a non-
standard custom image size.
This register is read-only.
Format:
Field
Presence_Inq
Num_Cols
Num_Rows
V_Pre_Color
H_Pre_Color
V_Post_Color
H_Post_Color
V_Bin
H_Bin
V_Bayer_Bin
H_Bayer_Bin
A.3.2

Inquiry Registers for Custom Video Mode Offset Addresses

The following set of registers indicates the locations of the custom video mode base registers. These offsets are
relative to the base offset 0xFFFF F0F0 0000.
Revised 9/27/2012
Copyright ©2011-2012 Point Grey Research Inc.
Bit
Presence of this feature
[0]
0: Not Available, 1: Available
[1-7] Reserved
Number of columns being binned/subsampled, minus 1
[8-11]
(e.g., if combining 4 columns together, this register will report a value of 3)
Number of rows binned/subsampled, minus 1
[12-15]
(e.g., if combining 4 columns together, this register will report a value of 3)
[16-23] Reserved
Vertical subsampling/downsampling performed before color processing
[24]
0: Off, 1: On
Horizontal subsampling/downsampling performed before color processing
[25]
0: Off, 1: On
Vertical subsampling/downsampling performed after color processing
[26]
0: Off, 1: On
Horizontal subsampling/downsampling performed after color processing
[27]
0: Off, 1: On
Standard vertical binning (addition of adjacent lines within horizontal shift register)
[28]
0: Off, 1: On
Standard horizontal binning (addition of adjacent lines within horizontal shift register)
[29]
0: Off, 1: On
Vertical bayer binning (addition of adjacent even/odd lines within the interline transfer buffer)
[30]
0: Off, 1: On
Horizontal bayer binning (addition of adjacent even/odd columns within the horizontal shift
[31] register)
0: Off, 1: On
Appendix A: Control and Status Registers
Description
144