Analog Devices ADSP-BF59x Blackfin Hardware Reference Manual page 761

pulse width modulation mode, See
PWM_OUT mode
pulse width modulation mode, See
PWM_OUT mode
pulse width modulator,
PWM_CLK clock, 8-20
PWM_CLK signal, 8-20
PWM_OUT mode, 8-10
control bit and register usage,
error prevention, 8-44
externally clocked, 8-20
PULSE_HI toggle mode,
stopping the timer, 8-21
Pxn bit, 7-22
Pxn both edges bit, 7-26
Pxn direction bit, 7-22
Pxn input enable bit, 7-23
Pxn polarity bits, 7-25
Pxn sensitivity bit, 7-26
Q
quick boot, 16-25
R
RBC bit, 5-37, 5-83
RBSY flag, 13-41
RBSY (receive error) bit,
RCKFE (clock falling edge select) bit,
14-32, 14-52, 14-55
RCVDATA16[15:0] field,
RCVDATA8[7:0] field,
RCVFLUSH (receive buffer flush) bit,
12-36, 12-37
RCVINTLEN (receive buffer interrupt
length) bit, 12-36
RCVSERVM (receive FIFO service
interrupt mask) bit,
RCVSERV (receive FIFO service) bit,
12-40, 12-41
ADSP-BF59x Blackfin Processor Hardware Reference
1-13
to 8-23, 8-43
8-45
8-15
13-39
12-46
12-45
12-40
RCVSTAT[1:0] field,
RDTYPE[1:0] field, 14-27, 14-52,
read/write access bit, 2-5,
receive buffer[7:0] field,
receive configuration (SPORTx_RCR1,
SPORTx_RCR2) registers,
receive data[15:0] field,
receive data[31:16] field,
receive data buffer[15:0] field,
receive FIFO, SPORT,
reception error, SPI, 13-41
register-based DMA, 5-9
registers
See also registers by name
system, A-2
REP bit, 5-38, 5-83
request data control command, DMA,
request data urgent control command,
DMA, 5-34
reset
effect on SPI, 13-15
RESET_DOUBLE bit,
RESET pin, 16-4
resets
core and system, 16-71,
core double-fault, 16-4
core-only software, 16-4
hardware, 16-3, 16-6
interrupts, 16-6
power-on, 16-3
software, 16-5
system software, 16-3
watchdog timer, 16-3,
RESET_SOFTWARE bit,
reset vector, 16-1
RESET_WDOG bit, 10-5,
restart control command, DMA, 5-32,
5-33
restart or finish control command,
transmit, 5-34, 5-35
Index
12-38
14-54
2-6
11-26
14-51
14-60
14-60
13-42
14-58
5-34
16-52
16-72
16-5
16-52
16-52
I-23