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Portwell NANO-5050 User Manual

Portwell nano-5050 nano-itx board
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NANO-5050
NANO-ITX Board
User's Manual
Version 1.0
Copyright © Portwell, Inc., 2013. All rights reserved.
All other brand names are registered trademarks of their respective owners.

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  • Page 1 NANO-5050 NANO-ITX Board User's Manual Version 1.0 Copyright © Portwell, Inc., 2013. All rights reserved. All other brand names are registered trademarks of their respective owners.

  • Page 2: Table Of Contents

    Preface Table of Contents How to Use This Manual Chapter 1 System Overview.......................1-1 1.1 Introduction..........................1-1 1.2 Check List ............................. 1-1 1.3 Product Specification ........................1-1 1.4 System Configuration ......................... 1-3 1.4.1 Mechanical Drawing......................1-4 1.5 System Architecture ........................1-5 Chapter 2 Hardware Configuration ...................2-1 2.1 Jumper Setting ..........................

  • Page 3: How To Use This Manual

    Preface How to Use This Manual The manual describes how to configure your NANO-5050 system to meet various operating requirements. It is divided into five chapters, with each chapter addressing a basic concept and operation of Single Board Computer. Chapter 1 : System Overview. Presents what you have in the box and give you an overview of the product specifications and basic system architecture for this series model of single board computer.

  • Page 4: Chapter 1 System Overview

    System Overview Introduction Portwell Inc., a world-leading innovator in the Industrial PC (IPC) market and a member of the Intel® Communications Alliance, has launched its new NANO-ITX form factor based NANO-5050 for embedded system board (ESB) that offers a smaller footprint, lower power consumption, robust computing power and with longevity support.
  • Page 5 - On-board programmable 8-bit Digital I/O interface Cooling Fans - Support one 3-pin power connector for system fan System Monitoring Feature - Monitor system temperature and major power sources. Outline Dimension (L x W) - 120mm(4.72’’) x 120mm(4.72’’) NANO-5050 User’s Manual...

  • Page 6: System Configuration

    System Overview System Configuration System Configuration CPU Type Intel® Atom™ CPU D2550 @1.86GHz L2:1024K SBC BIOS Portwell, Inc. NANO-5050 Rev.:R1.00.W2(12112012) Memory Transcend DDR3 1066 SODIMM 4G*1 (hynix H5TQ2G83AFR) VGA Card Onboard Intel® Graphics Media Accelerator 3600 Series VGA Driver Intel® Graphics Media Accelerator 3600 Series Ver:8.14.8.1075 LAN Card Onboard Intel®...

  • Page 7: 1.4.1 Mechanical Drawing

    System Overview 1.4.1 Mechanical Drawing NANO-5050 User’s Manual...

  • Page 8: System Architecture

    System Overview System Architecture All of details operating relations are shown in NANO-5050 System Block Diagram. NANO-5050 System Block Diagram NANO-5050 User’s Manual...

  • Page 9: Chapter 2 Hardware Configuration

    Hardware Configuration This chapter gives the definitions and shows the positions of jumpers, headers and connector. All of the configuration jumpers on NANO-5050 are in the proper position. The default settings are indicated with a star sign ( ). Jumper Setting In the following sections, Short means covering a jumper cap over jumper pins;...

  • Page 10: Connectors

    Hardware Configuration Figure 2-2 NANO-5050 Jumper and Connector Locations (Bottom) Connectors I/O peripheral devices are connected to the interface connectors. Connector Function Remark +12V DC adapter Line Out Mic In Display Port CRT display NANO-5050 User’s Manual...
  • Page 11 LVDS Back-light enable level high/low (Default 1-2) Pin Assignments of Connectors J1 : reserve for +12V DC adapter PIN No. Signal Description J2 : Line Out PIN No. Signal Description Line Out L Jack Detect Line Out R NANO-5050 User’s Manual...
  • Page 12 Lane2+ Lane2- Lane3+ Lane3- CONFIG1 CONFIG2 AUX_CH+ AUX_CH- Hot Plug Return for Power DP Power 3.3V/500mA J5 : CRT Display PIN No. Signal Description PIN No. Signal Description DDCCLK GREEN A_Ground BLUE DDCDATA VSYNC D_Ground HSYNC DDC_VCC NANO-5050 User’s Manual...
  • Page 13 J8/J9 : reserve USB PIN No. Signal Description PIN No. Signal Description USBD- USBD- USBD+ USBD+ J10 : 8 bits GPIO PIN No. Signal Description PIN No. Signal Description GPIO0 GPIO4 GPIO1 GPIO5 GPIO2 GPIO6 GPIO3 GPIO7 NANO-5050 User’s Manual...
  • Page 14 TxD-/RxD- TxD+/RxD RxD+(422 only) RxD-(422 only) J13 : +12V DC Source PIN No. Signal Description +12V +12V J14 : Reserve J15 : Mini PCIe PIN No. Signal Description PIN No. Signal Description Wake# 3.3V Reserved Reserved 1.5V NANO-5050 User’s Manual...
  • Page 15 LED_WAN# Reserved LED_LAN# Reserved LED_PAN# Reserved 1.5V Reserved Reserved 3.3V J16 : Rear Side FAN 1 2 3 PIN No. Signal Description Ground +12V Fan Speed Detecting signal J17 : SATA Power PIN No. Signal Description +12V NANO-5050 User’s Manual...
  • Page 16 PIN No. Signal Description PIN No. Signal Description WR_LED- LVDS_DATA#0 SUS_LED+ LVDS_DATA#1 HDD_LED+ HDD_LED RST_BTN PWR_BTN J20 : SATA PIN No. Signal Description DF_SATA_TX+0 DF_SATA_TX-0 DF_SATA_RX-0 DF_SATA_RX+0 J21 : SM BUS PIN No. Signal Description SM_CLK SM_DATA 3.3V NANO-5050 User’s Manual...
  • Page 17 DF_ PCIE_CLKN2 DF_PCIE_RXP2 DF_PCIE_RXN2 +3.3V +3.3V CLKREQ2# +3.3V +3.3V_AUX RST# PCIE_WAKE# SMBDATA DF_ PCIE_CLKP1 DF_ PCIE_CLKN1 DF_PCIE_TXP1 DF_PCIE_TXN1 DF_PCIE_RXP1 DF_PCIE_RXN1 CLKREQ1# J25 : CF-SATA PIN No. Signal Description PIN No. Signal Description CD1# CS0# CS1# VS1# ATASEL# IOR# NANO-5050 User’s Manual...
  • Page 18 PDIAG# IOCS16# CD2# JP1 : Clean RTC PIN No. Function Positive Negative JP2 : Panel Power Level PIN No. Process Selection 3.3V JP3 : Backlight enable signal type PIN No. Process Selection High enable Low enable NANO-5050 User’s Manual 2-10...

  • Page 19: Chapter 3 System Installation

    Step 1 : Check all jumpers setting on proper position Step 2 : Install memory module onto memory socket Step 3 : Place NANO-5050 into the dedicated position in the system Step 4 : Attach cables to existing peripheral devices and secure it WARNING Please ensure that SBC is properly inserted and fixed by mechanism.

  • Page 20: Chipset Component Driver

    3.3.1 Chipset Component Driver The chipset on NANO-5050 is a new chipset that a few old operating systems might not be able to recognize. To overcome this compatibility issue, for Windows Operating Systems such as Windows 7, please install its INF driver before any other drivers installation.

  • Page 21: Clear Cmos Operation

    0x07); outportb(0x2F, LDN); void set_CFG (unsigned char Add, unsigned char Value) outportb (0x2E, Add); outportb (0x2F, Value); int main(void) unsigned char temp; // Initialze WDT function temp = get_CFG (0x2D) & ~0x01; set_CFG (0x2D, temp); change_LDN (0x08); NANO-5050 User’s Manual...
  • Page 22 (0xF7, 0x00); printf ("Trigger WDT with 5 sec...will reboot in 5 sec.\n"); printf ("Press Enter to disable WDT...\n"); set_CFG (0xF6, 0x05); getchar (); set_CFG (0xF6, 0x00); printf ("All test complete. Press Enter to EXIT."); getchar(); return 0; NANO-5050 User’s Manual...

  • Page 23: Gpio

    I/O function. GPIO Pin Assignment The NANO-5050 provides 8 input/output ports that can be individually configured to perform a simple basic I/O function. Users can configure each individual port to become an input or output port by programming register bit of I/O Selection. To invert port value, the setting of Inversion Register has to be made.
  • Page 24 (unsigned char Add, unsigned char Value) outportb (0x2E, Add); outportb (0x2F, Value); void main (void) unsigned char tmpData = 0x0; printf("==== NANO-5050 GPIO test program ====\n"); enter_SIO(); // Initialze GPIO function set_cfg (0x2C, get_cfg (0x2C) & ~0xE0; ); // Switch to LDN9 for GPIO3 change_LDN(0x09);...
  • Page 25 = get_CFG(0xF1); // printf("data: 0x%X ", tmpData); if(tmpData == 0xFF) printf("PASS!\n"); else printf("FAIL!\n"); // printf("Set GP1~4 LOW\n"); set_CFG(0xF1, 0x00); // printf("Read GP5~8:"); tmpData = get_CFG(0xF1); // printf("data: 0x%X ", tmpData); if(tmpData == 0x00) printf("PASS!\n"); else printf("FAIL!\n"); getchar(); NANO-5050 User’s Manual...

  • Page 26: Chapter 4 Bios Setup Information

    Chapter 4 BIOS Setup Information NANO-5050 equipped with the Phoenix BIOS stored in SPI Flash. BIOS has built-in setup program that allows users to adjust the basic system configuration. This type of information is stored in CMOS RAM that it is retained even if power-off periods.

  • Page 27: Main

    BIOS Setup Information Main Once you enter NANO-5050 Phoenix BIOS CMOS Setup Utility, a Main Menu is presented. The Main Menu allows user to select from eleven setup functions and two exit choices. Use arrow keys to switch among items and press <Enter> key to accept or bring up the sub-menu.

  • Page 28: Configuration

    BIOS Setup Information Configuration This section allows users to configure further BIOS function. Boot Configuration NANO-5050 User’s Manual...
  • Page 29 ‘Disabled’ the diagnostic splash screen dose not display unless you press HOTKEY during boot. The choice: Enabled, Disabled. Diagnostic Summary Screen Display the Diagnostic summary screen during boot. The choice: Enabled, Disabled. UEFI Boot Enables the UEFI Boot. The choice: Enabled, Disabled. PCI/PCIE Configuration NANO-5050 User’s Manual...
  • Page 30 BIOS Setup Information PCH PCI Express Configuration DMI Link ASPM Control The control of active state Power Management on both NB side of the DMI Link. Choices: Enabled, Disabled. PCI Express Root Port 1~4 NANO-5050 User’s Manual...
  • Page 31 Enable or disable Root PCI Express System Error on Fatal Error. SENFE Root PCI Express System Error on Non-Fatal Error Enable/Disable. SECE Root PCI Express System Error on Correctable Error Enable/Disable. PME Interrupt Root PCI Express PME Interrupt Enable/Disable. NANO-5050 User’s Manual...
  • Page 32 Wake System With Fixed Time Enable or disable System wake on alarm event. When enabled, System will wake on the hr::min::sec specified. Choices: Enabled, Disabled. Wake up By Ring Enable or disable Ring to wake the system. Choices: Enabled, Disabled. NANO-5050 User’s Manual...
  • Page 33 Select the number of physical cores to enable in each processor package. Choices: 1, All. Execute Disable Bit Enable Execute Disabled functionality. Also known as Data Execution Prevention (DEP). Local x2APIC Enable Local x2APIC. Some 0Ses do not support this. Choices: Enabled, Disabled. NANO-5050 User’s Manual...
  • Page 34 LAN Control LAN Control Enabled/Disabled. Choices: Enabled, Disabled. Wake on LAN Enable or disable integrated LAN to wake the system. Choices: Enabled, Disabled. LAN Boot ROM Enable or disable integrated LAN Boot ROM(PXE) function. Choices: Enabled, Disabled. NANO-5050 User’s Manual...
  • Page 35 BIOS Setup Information Chipset Configuration VT-d Check to enable VT-d function on MCH. Choices: Enabled, Disabled. Azalia Control Detection of the Azalia device. Choices: Enabled, Disabled. NANO-5050 User’s Manual 4-10...
  • Page 36 To Enable the PEG Slot. Choices: Enabled, Disabled. PEG ASPM Control ASPM Support for the PEG Device. This has mp effect if PEF is not the current active device. Choices: Disabled, Auto, ASPM L0s, ASPM L1, ASPM L0sL1. NANO-5050 User’s Manual 4-11...
  • Page 37 BIOS Setup Information Memory Configuration Graphic Configuration NANO-5050 User’s Manual 4-12...
  • Page 38 Select LCD Panel used by internal Graphics by selecting the appropriate setup item. Choices: 800x600, 1024x768, 1280x800, 1280x1024, 1920x1080 Backlight Control Choices: Level 1, Level 2, Level 3, Level 4, Level 5, Level 6, Level 7. SATA Configuration NANO-5050 User’s Manual 4-13...
  • Page 39 Display the identity of the device attached. USB Configuration Legacy USB Support Enable Legacy USB support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB device available only for EFI applications Choices: Enabled Disabled. NANO-5050 User’s Manual 4-14...
  • Page 40 BIOS Setup Information PCH USB Configuration UHCI Controller #1~#3 Control each of the USB Controller(1~4) Choices: Enabled, Disabled CF-SATA Enable CF-SATA Enable/Disable. Choices: Enabled, Disabled. NANO-5050 User’s Manual 4-15...
  • Page 41 BIOS Setup Information SIO Configuration NANO-5050 User’s Manual 4-16...
  • Page 42 Choices: Disable, 15secs, 30secs, 1min, 2mins, 3mins Hardware Monitor SYS1 Target Temp: SYS1 FAN Target Temperature Choices: Disable, 40°C, 45°C, 50°C, 55°C. SYS1 Tolerance Temp: CPU FAN Tolerance Temperature Choices: Disable, 5°C, 4°C, 3°C, 2°C, 1°C. NANO-5050 User’s Manual 4-17...
  • Page 43 BIOS Setup Information Serial Port Console Configuration Console Redirection Console Redirection Enable or Disable Choices: Enabled, Disabled NANO-5050 User’s Manual 4-18...
  • Page 44 VT100+ and then VT100. See above, in console Redirection Settings page, for more Help with Terminal Type/Emulation. The choice: VT100, VT100+, VT-UTF8, ANSI Bits Per second Select serial port transmission speed The choice: 9600, 19200, 57600, 115200. NANO-5050 User’s Manual 4-19...

  • Page 45: Security

    Set or Clear Supervisor Password Supervisor Hint String Press Enter to type Supervisor Hint String Min. password length Set the minimum number of characters for password (1-20). Flash Controller Lock Lock all flash controllers The choice: Enabled, Disabled. NANO-5050 User’s Manual 4-20...

  • Page 46: Boot

    <Enter> to enter the sub-menu. Then you may use the arrow keys (↑↓) to select the desired device, then press <＋>, <－> or <PageUp>, <PageDown> key to move it up/down in the priority list. The choice: 1st FLOPPY DRICE, Disabled. NANO-5050 User’s Manual 4-21...

  • Page 47: Exit

    Equal to F9. Load standard default values. Discard Changes Load the original value of this boot time. Not the default Setup value. Save Changes Save all changes of all menus, but do not reset system. options. NANO-5050 User’s Manual 4-22...

  • Page 48: Chapter 5 Troubleshooting

    Hardware Quick Installation There are two methods to connect the power of NANO-5050 which are 12V DC Jack & 4 Pins 12V DC input. It’s able to be chosen either one for NANO-5050. Can be referred as the picture shows blew.

  • Page 49: Fqa

    BIOS setting that Portwell has highly endorsed. As a matter of fact, users can load the default BIOS setting any time when system appears to be unstable in boot up sequence.
  • Page 50 Extended BIOS Area 9E00-9FFF Unused A000-AFFF 64 K VGA Graphics B000-B7FF 32 K Unused B800-BFFF 32 K VGA Text C000-CF3F 61 K Video ROM CF40-EFFF 131 K Unused F000-FFFF 64 K System ROM 64 K First 64K Extended NANO-5050 User’s Manual...
  • Page 51 Usable IRQ 【Unassigned】 IRQ 10 Usable IRQ 【Unassigned】 IRQ 11 Usable IRQ 【Unassigned】 IRQ 12 System ROM IBM Mouse Event IRQ 13 System ROM Coprocessor Error IRQ 14 System ROM Hard Disk Event IRQ 15 Usable IRQ 【Unassigned】 NANO-5050 User’s Manual...

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