Vertical And Horizontal Sync Circuit Description - Ceronix 1493 Service Manual

VERTICAL AND HORIZONTAL SYNC CIRCUIT DESCRIPTION.

Vertical Sync
{
Composite
Horizontal Sync
Sync
Composite sync or separate vertical and horizontal sync
are buffered by two comparators in the sync interface
circuit. A vertical sync synchronization circuit is used to
insure a stable raster and functions as a sync separator.
1.8K
GND
328
H V
s
s
VC
VC
Horizontal
1
2
Sync
The sync interface comparators are biased to .15 volts,
by resistors & , to permit receiving low level
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sync signals such as RS170. For low level composite
sync, the vertical and horizontal lines are tied together
and jumper is left off. For normal amplitude sync,
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(greater than 2.3 volts) resistors
attenuator to protect the sync interface comparators and
normalize the sync amplitude. This combination also
reduces noise sensitivity since the sync voltage amplitude
is low at the comparator input which slows the
comparator response and acts as a low pass filter.
For the interlaced sync case, the pullup resistor
left off and the voltage divider resistors
as the pullup. Also the vertical sync synchronization
comparators are disabled by changing the input resistors
to bias the comparators in the high output state and
resistor is left off. Capacitor
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separator for composite interlaced sync. Capacitor
and jumper are used to couple the composite sync to
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the LA7851 vertical sync input pin 19.
The vertical sync synchronization window comparator
generates a pulse, a little after the midpoint of each
horizontal cycle. This pulse is shorted to GND by
transistors except when vertical sync is active. The
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two transistor circuit permits using either positive or
negative pulses for vertical sync.
78
Sync Interface
2 Comparators
Vertical Sync
0Ω
Interlace (15KHz)
364
10uF
+
259
1K 1.8K 0Ω
246 47nF 257 318
254
+12V
22K
323
4
3
325 1/4
270Ω LM339
5
355
326
+
0Ω
6
270Ω
1/4
330 LM339
1.8K
7
355
+
12
331
.14-.16V
270Ω
327
Vertical
Sync
GND
& form an
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325 326
and
246 246 257 257
acts as a sync
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For Interlaced Vertical Sync.
Vertical Sync To Horizontal Cycle Synchronization
and Composite Sync Decoder
The synchronization circuit is bypassed, for interlaced
vertical sync, because this circuit rejects the half
horizontal line time variation used to generate the
interlaced vertical raster.
Horizontal Sync
+12V
7.15K
366
1/4
7.15K 14
LM339
364
355
1.5-2VDC 59,D6
13 1/4
LM339
355
6.8K
321
6.8K
200K
322
246
2
PN2222
255
1
100K
257
.047uF
200K
256
318
GND
Capacitor
318
318
transistors
254 254
transistor
255 255
negative vertical sync pulse, transistor
by the negative pulse applied to resistor
window comparator pulse is allowed to be the vertical sync
pulse. For positive vertical sync pulse, transistor
turned on by resistor
of transistor
255 255
comparator pulse to act as the sync pulse.
A sawtooth waveform is produced on integrating
is capacitor
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act & . This sawtooth waveform is connected to two
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comparators which are biased by resistors
, , &
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354
high between 1.8 volts to 2.3 volts. This circuit would
produce a pulse on both the positive and negative slope
parts of the sawtooth waveform. Resistor
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the output pulse on the negative slope by introducing part
of the flyback pulse to pin 8 which keeps the comparator
from going high at this time. Resistors
a pullup for the window comparator and apply a 6 volt bias
to the vertical sync input, LA7851 pin 19. At 6 volts, the
vertical sync input is inactive. It becomes active only
when the window comparator output and the ± sync
transistors are all high.
+
FBP
9
+
68.1K 15.8K
15.8K
353 354 360
8
2.1-2.4VDC Hs
4.6Vpp 58,D6
1K
357
11
+
10
3.92K
358
356
Vs,Hs
.05VDC
7V pp 60,C5
PN2222
254
33K
247
couples the vertical sync pulses to
& . When no sync pulse is present,
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is turned on by resistor
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255 255
& , which shorts the base
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to GND also allowing the window
by applying the flyback pulse to resistors
such that both comparator outputs are
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To LA7851 pin 19
To LA7851 pin 1
. For a
is turned off
and the
257
257
is
254 254
,
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eliminates
357 357
& act as
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364 366