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Pin No.
Symbol
63
LWR#
64
LOE#
65~67
LCS[3,1,0]#
68~79
LA[0:17]
80
VSS
81
VPP
82~87
LA[0:17]
88
ACLK
89
AOUT
SEL_PLL0
90
ATCLK
91
ATFS
SEL_PLL1
92
MA9
DOE#
93
AIN
94
ARFS
95
ARCLK
96
TDMCLK
97
TDMDR
98
TDMFS
99
CAS#
100
VSS
I/O
O
RISC interface write enable (active-low).
O
RISC interface output enable (active-low).
O
RISC interface chip select (active-low).
O
RISC interface address.
I
Ground.
I
5.0V power supply.
O
RISC interface address.
I/O
Master clock for external audio DAC (8.192MHz, 11.2896MHz,
12.288MHz, 16.9344MHz, and 18.432MHz).
O
Audio interface serial data.
I
Used with SEL_PLL1 pin 91 to select phase-lock loop (PLL) clock
frequency of CPUCLK pin 42:
00 = bypass PLL.
01 = 54MHz PLL.
10 = 67.5MHz PLL.
11 = 81MHz PLL.
I/O
Audio transmit bit clock.
O
Audio interface transmit frame sync.
I
Used with SEL_PLL0 pin 89 to select phase-lock loop (PLL) clock
frequency of CPUCLK pin 42,
O
Multiplexed memory row and column address.
O
Memory output enable (active-low).
I
Audio interface serial data.
I
Audio receive bit clock.
I
Audio interface receive frame sync.
I
TDM serial clock.
I
TDM serial data receive.
I
TDM frame sync.
O
Memory colomn address strobe (active-low).
I
Ground.
Descriptions
(No.22041)1-49
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