Display Memory; Nonvolatile Memory; Keyboard Interface; Video Control - Wyse WY-60 Maintenance Manual

AUX
port--The AUX port is controlled by the UART within 8051,
pins 4, 5, 10, and 11. Pin 4 of t.he 8051 is reserved for data
set ready signals, Pin 5 is reserved for data terminal ready
singal. Pins 10 and 11 transmit and receive data. The MC1488
driver (U27) and the MC1489A receiver (U28) are both RS232
compatible. The 8051 itself converts parallel logic PCB data to
bit-serial data, while adding stop, start, and parity bits. The
serial format is transmitted at user-selected baud rate.
Display Memory
The display memory in the terminal is dual-ported between the CRT
controller and the 8051. There are two 8Kx8 RAM chips installed
for single-page operation. During the first scan line of each
character row, the 2672 PVTC sends an interrupt on INTO of the
8051 nine microseconds before starting a DMA transfer from the
display RAM. The 8051 cannot access the display RAM, the 2672,
or the 2661 during DMA transfers. The 8051 does not stop during
the DMA transfer, but cannot access other external devices.
Nonvolatile Memory
The terminal stores all configuration parameters in the
nonvolatile EEPROM (U2). The memory operates from the +5 volt
supply. Address and data information are clocked into the EEPROM
through bidirectional SDA pin 5. Pin 6 is the clock
synchronizing clock pin 5.
Keyboard Interface
Each key on the keyboard is tested for key depression by
advancing the keyboard row/column counter to its address, then
testing the line on the 8051. At least six microseconds elapse
between outputting an address and testing the key return.
Debouncing and multiple key depressions are handled by the 8051.
Video Control
Video control consists of the video clock circuitry, programmable
video timing controller, attribute control, character generator,
and video shift register.
Video Clock Circuitry--Either a 26.580 MHz (Xl, for 80-column
mode) or a 39.710 MHz oscillator (X2, for 132-column mode)
generates timing for the dot clock and character clock. Both are
TTL versions of Pierce oscillators.
Both oscillators are enabled by pin 1 from t~e 8051. Pin 1 is
the 80/132 column switch line. Once enabled, the 39.710 MHz
oscillator generates a 132-column display. The 26.580 MHz
oscillator generates an 80-column display.
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