Clock Rates - Wyse WY-60 Maintenance Manual

Clock Divider--The 8051 selects the oscillator frequency
that goes to the gate array. The gate array divides these
frequencies to generate specific clock rates. Table 6-1
lists original dot clock rate (oscillator frequencies),
number divided by, the rate it becomes after division, and
what it controls.
Table 6-1
Clock Rates
Beginning
New Clock
Clock Rate
Divisor Rate New Clock
39.710 MHz
9
4.4122 MHz CCLK
( 132 - col urn n mod e )
26.580 MHz 10 2.658 MHz
CCLK
(SO-column mod e)
Programmable video timing controller (U9}--The microcontroller
initializes the programmable video timing controller (PVTC)
during power-up. The CRT controller interfaces with the video
display memory (RAM) on a direct-memory access (DMA) basis.
Display data then moves to the character generation circuitry for
processing. The CRT controller chip (PVTC) generates the cursor
and also provides the necessary timing and control information
for the display logic: horizontal synchronization, vertical
synchronization, and blank.
UART (U3)--The universal asynchronous receiver/transmitter (UART)
takes parallel data from the microprocessor and converts it to a
bit-serial format for external communication equipment through
the MODEM port. In addition, the UART converts bit-serial
information received from an external source to parallel
information for the microprocessor. The UART flags the
microcontroller with an interrupt when it needs service.
Code ROM (U6)--The code ROM is nonvolatile memory for program
storage. All routines reside in ROM. The terminal ROM can be
either 32 or 64K bytes (60KB maximum available for storage),
depending upon PROM type, either the 27256 or 27512. The ROM
does not reside within the RAM memory map because it has a unique
enable line (PSEN).
Chip select decoder (U5)--The chip select decoder decodes the
higher order address bits (A13, A14, A15) and the Read and Write
control lines (RD and WR) from the microcontroller. The decoder
generates enable signals for the character RAM, UART, and PVTC.
Low order address latch (U4)--This IC latches and gates the lower
order address information from the microcontroller when activated
by the microcontroller's address latch enable (ALE) signal. The
latch separates data from the address bus when data is present on
the microcontroller's multiplexed lower address and data bus
interface.
6-4