Pll Circuit (2) - Toshiba TLP411E Technical Training Manual

+5 VD
V BLK
ZX15
TEM2026D
Clock
output
Inside
Outside
ZX16
TEM2026D
ZX17
TEM2026D

2-8. PLL Circuit (2)

TLC2932IPW (QX42) is used in the PLL circuit. The pin
configuration is shown in Fig. 6-20, the terminal functions
are in table 6-8 and the internal block diagram is shown in
Fig. 6-21.
The circuit diagram of PLL circuit is shown in Fig. 6-23.
The IC is composed of a VCO able to oscillate in 20 – 60
MHz and PFD. In this unit, a rag-read type loop filter is
provided by combining the IC and CRs. The center fre-
quency of VCO varies depending on the constant value of
RX88 and the lock enable frequency is approx. 23 – 40
MHz when the RX88 is 3.3 kW .
VHB (pin 10) and PIHB (pin 9) are the terminals to stop
the VCO/PFD operation. To display signal sent from the
personal computer, the IC operation is stopped by making
these terminals Hi.
LOGIC V 1
DD
TEST 2
VCO OUT 3
F -A 4
IN
F I -B 5
N
PFD OUT 6
LOGIC GND 7
Fig. 6-20 Pin configuration of TLC2932IPW
LX21
TEM2103T
CX58 CX61
0.33 0.33
1 VD-D
2
NC
RX77 47
3
VCOO
4
FI-A
5
FI-B
RX78 330
6
PFDO
7
DG
RX79 330
QX38
TLC2933IPW
RX80
Fig. 6-19 PLL Circuit (1) circuit diagram
14 VCO V
DD
13 R
BIAS
12 V
COIN
11 VCO GND
10 VCO INHIBIT
9 PFD INHIBIT
8 NC
CX62
16V
10
RX82
3.3k
VD-A 14
13
RBIAS
12
VCIN
11
AG
10 CY21
VIHB
0.01
PIHB 9
8
NC
RY44 560
1k
F -B
IN
LOGIC V
DD
INHIBIT
1 5
PFD
7 4
F -A
IN
LOGIC GND
Fig. 6-21 TLC2932IPW internal block diagram
6-15
QX52
MC33078M
8 7 6 5
RY42
10k
1 2 3 4
CY19
CY22
16V
0.1
0.33
RY43
10k
TEM2103T
CY23
16V
10
COUNTER
VCO V VCO OUT
DD
PFD VCO
INHIBIT
SELECTOR
9 10 14 3
1/2 DIVIDER
VCO
6 12 13
PFD OUT
R
LPF VCO IN
LX22
2
11
BIAS
VCO GND