Digital Circuit Operation; Display Mode - Toshiba TLP411E Technical Training Manual

1. DIGITAL CIRCUIT OPERATION

In the digital circuit, the following operations are carried
out; video signal double speed conversion/enlargement pro-
cess (NTSC signal), sync generation/Various kinds of tim-
ing signal generation necessary for liquid crystal panel driv-
ing and on-screen signal generation. Fig. 6-1 shows the
digital circuit block diagram.
R SIGNAL
CLAMP
IN
G SIGNAL
CLAMP
IN
B SIGNAL
CLAMP
IN
CLP PULSE
VD
TC160G54AF1137
HD
(QX38, QX52)
40 - 85 MHz
A/D (QX16) FIELD MEMORY (QX19)
A/D (QX17) FIELD MEMORY (QX20)
FIELD MEMORY (QX21)
A/D (QX18)
WCK (=1/4 CLK1)
WRS, WLRS
CLK2
CLR
EPM7032
FIOE
PLD
(QX41)
SYG
(QX32)
1/8 CLK1
HD (FOR OSD)
HD, VD
1/4 CLK1
CLOCK
DIVIDER
PLL1
CLK1
(QX39, QX40)
Fig. 6-1 Digital circuit block diagram

1-1. Display Mode

This unit uses a liquid crystal panel with 832 x 624 pixels.
Basically, the effective pixel number (scanning line num-
ber) in the vertical direction is specified as the display pixel
number in the vertical direction and the display pixel num-
ber in the horizontal direction is determined in relation to
the aspect ratio of the signal system used.
Accordingly, The display area displayed on the panel dif-
fers owing to the input signal and the area not displayed is
masked. The masked area is generated by writing the mode
signal for the liquid crystal panel during the blanking pe-
riod.
Accordingly, the signal supplied to the liquid crystal
panel is a usual non-interlace signal and any blanking
period is not added. For more details, refer to item 2-8
in section 4 (Page 4-7).
D/A
(QX22)
CLK2
PLL2
(QX42) (QX43)
CLK2
TIMING GENERATOR
PCLK
FOR LCD PANEL
(QX45)
6-2
R SIGNAL
BUFFER
OUT
G SIGNAL
BUFFER
OUT
B SIGNAL
BUFFER
OUT
OSD
OSD SIGNALS
(R G B SEL)
TIMING PULSE
FOR
LCD PANEL
BUS SIGNALS