Toshiba TLP411E Technical Training Manual
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Toshiba TLP411E Technical Training Manual

Toshiba TLP411E Technical Training Manual

3 lcd data projector
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FIE NO. 336-9612
TECHNICAL TRAINING MANUAL
3 LCD DATA PROJECTOR
TLP411U
TLP411E
Dec., 1996

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  • Page 1 FIE NO. 336-9612 TECHNICAL TRAINING MANUAL 3 LCD DATA PROJECTOR TLP411U TLP411E Dec., 1996...

  • Page 2: Table Of Contents

    CONTENTS SECTION I 2-3. Level Shifter Circuit (Q965 – Q968, R1044) ....... 4-4 MAIN POWER SUPPLY 2-4. Black Limiter (Q969, Q970) ..... 4-4 CIRCUIT ......... 1-1 2-5. Inverted Signal Amplifiers (Q974 – Q981) ..........4-4 1. OUTLINE .........1-2 2-6. Switch Circuit 1-1.
  • Page 3 SECTION VI SECTION VIII DIGITAL CIRCUIT ....6-1 CCD CAMERA CIRCUIT ..8-1 1. DIGITAL CIRCUIT 1. OUTLINE .........8-2 OPERATION ........6-2 1-1. CCD and Drive/Sync Signal Generation Circuit (SG) ......8-2 1-1. Display Mode ..........6-2 1-2. Pre-amp Circuit (CDS) ......8-2 1-2.

  • Page 4: Section I

    SECTION I MAIN POWER SUPPLY CIRCUIT...

  • Page 5: Outline

    1. OUTLINE 2. DESCRIPTION ABOUT CIRCUIT OPERATION The power supply circuit operates on AC as input and outputs DC (+S6V, +6V, +10V, +12V, +15.5V) through 2-1. Surge Absorber Circuit inverter after rectification and smoothing of the AC power. The surge absorber circuit consists of protection element ON/OFF function is provided for outputs other than +S6V (varistor) and spark gap on the pattern surface on the PC by the external signal.

  • Page 6: Noise Filter Circuit

    2-2. Noise Filter Circuit 2-4. Smoothing/Rectifying Circuit The noise filter circuit only protects the noise generated The input voltage of the unit is set to work in the range of by the power source from leaking out to AC line and from AC100 ~ 120V and AC220 ~ 240V.

  • Page 7: Inverter Circuit (Flyback)

    2-6. Primary Control Circuit The half-wave rectification for V is carried out by IN (AC) C and Di (D007) shown in the dotted line ----. When the The control system employs automatic flyback system by input voltage is low, the triac is turned on (voltage doubler timing capacitor.

  • Page 8: Secondary Rectification & Smoothing Circuit

    2-7. Secondary Rectification & Smoothing 2-9. +6V, +S6V, +15.5V Overvoltage Circuit Protection Circuit High-voltage applied to N becomes, as mentioned previ- As shown in Fig. 1-9, the overvoltage of +6V and +S6V ously, pulse by means of the switching operation and then is detected by ZD101 and the overvoltage +15.5V is de- converted to low voltage at both ends of the secondary tected by ZD401.

  • Page 9: S6V Over Current Protection Circuit

    2-10. +6V, +S6V Over Current Protection Circuit As shown in Fig. 1-12, this circuit detects the over current by differential amplifier consisting of Q102 and Q103. The reference voltage is produced by voltage division of R105 and R106 using the +S6V as voltage source. This voltage called VA (+S6V x R106/R105 + R106) is compared with Voltage VB (Ioc x R108) generated by over current.

  • Page 10: Lamp High Voltage Power Supply Circuit

    SECTION II LAMP HIGH VOLTAGE POWER SUPPLY CIRCUIT...

  • Page 11: Lamp High Voltage Power Supply

    1. LAMP HIGH VOLTAGE POWER SUPPLY The lamp high voltage power supply receives a DC220 to 390V (primary side) from the system power supply and provides a DC voltage (50 to 70V at ever turning on the lamp) to turn on the lamp. Fig. 2-1 shows the block dia- gram.

  • Page 12: Optical System

    SECTION III OPTICAL SYSTEM...

  • Page 13: Configuration

    1. CONFIGURATION Name Description Metal halide Light source of the optical system. DC system,250W, short arc length 3mm. lamp To use light effectively in the tilt projection system, the light axis is arranged to face upward. Lamp unit Elliptical Elliptical reflector converges light emitted from the metal halide-lamp, thereby creating light reflector beams parallel with light axis and illuminating the beams to the liquid crystal panel.
  • Page 14 10 f 10 e 10 d Part name Projection lens Liquid crystal panel (red) Liquid crystal panel (green) To Lamp Liquid crystal panel (blue) 10 b Phase difference plate + polarized plate 10 a Field lens Mirror box unit 10a-f Dichroic mirror Multi-lens B Cold mirror...
  • Page 15 Phase Incidence side Liquid Exit side Phase difference polarized crystal polarized difference plate plate panel plate plate (45 rotation) (90 rotation) (45 rotation) P-polarization S-polarization light P-polarization light S-polarization light light 22.5 22.5 S-polarization Exit side light polarizing Incidence direction side polarizing direction...

  • Page 16: Rgb Drive Circuit

    SECTION IV RGB DRIVE CIRCUIT...

  • Page 17: Outline

    1. OUTLINE This circuit is described using G process as an example and composed of level shifter, gamma (g), black limiter, inverted signal amplifier, sample & hold circuit and liquid crystal panel. A block diagram of the drive circuit is shown in Fig. 4-1. Q983 Normal CXA2504N...

  • Page 18: Gamma (G G G G G ) Circuit

    2-2. Gamma (g g g g g ) Circuit When the base of Q963 develops 3.55 V , the emitter of Q961 develops 4.25 V . In the signal area where the base The circuit consists of a current source consisting of R983, of Q963 is higher than 4.25V, the current of 7.7 mA is flown R984, Q954, full feedback amplifier Q955 –...

  • Page 19: Level Shifter Circuit (Q965 - Q968, R1044)

    2-3. Level Shifter Circuit 2-6. Switch Circuit (Q982 µPD74HC4066A) (Q965 – Q968, R1044) The normal and inverted signal outputs are switched for Q965 – Q967 works as a current source. Assuming that the every horizontal and vertical period. base voltage of Q965 is 1.76 V , the current 4.2 mA is The signal is inverted for one horizontal period and then flown into Q967 and the same current also flown into Q968.

  • Page 20: Sample & Hold Circuit

    2-7. Sample & Hold Circuit Each sample & hold operation is carried out on pins 18, 19, 20, 1, 2 & 3 and the re-sample & hold operations for The block diagram of the circuit is shown in Fig. 4-10 and 6CH are carried out together on pins 21 and 40.
  • Page 21 Current setting I DR BIAS OUT6 Level shifter BIAS IN56 OUT6 BIAS OUT5 Level shifter OUT5 BIAS IN34 BIAS OUT4 Level shifter OUT4 Vcc2 Vcc1 BIAS OUT3 BIAS IN12 Level shifter OUT3 BIAS OUT1 Level shifter OUT2 I SH BIAS OUT1 Level shifter OUT1 Vcc3...

  • Page 22: Lcd Panel

    2-8. LCD Panel 2-8-1. Features • Number of dots displayed: 519,000 dots in diagonal The LCD panel uses the active matrix panel with 3.3 cm in length of 3.3 cm (1.3 type) diagonal length and a built in driver made of the super thin film multi-crystal silicone transistor.
  • Page 23 The liquid crystal panel is provided with a built in display area variable circuit inside the liquid crystal panel. It is possible to correspond with each signal of MAC16/SVGA/ VGA/PC98/NTSC/WIDE/PAL. The mode switching de- scribed above is carried out owing to the signal developed at pins 10 to 12 of the display area switch input terminal as shown in Fig.
  • Page 24 Table 4-1 Liquid crystal panel terminal description Symbol Description Symbol Description Uniformity improvement signal input terminal Start pulse input terminal for H shift resistor PSIG 11.5V driving 2.5V Video signal 4 input terminal to LCD panel, 7V SIG4 HCK1 Clock input terminal for H shift resistor driving center ±...

  • Page 25: Microcomputer

    SECTION V MICROCOMPUTER...

  • Page 26: System Outline

    1. SYSTEM OUTLINE Adjustment control • Video controls (high & low brightness ratio, The system microcomputer has features as shown below. brightness, color density, tint, sharpness) In considering easy maintenance for specification modifi- • Panel adjustments (V position, H position, phase, cation, etc.
  • Page 27 GAIN SYNC PL004 PL002 PL003 CONTRAST MODE FOCUS/ZOOM VOLUME/MUTE FAN. PW BRIGHT QL04 QL06 Q543 Q540 MM1096BS CXA1315M CXA1315M CXA1315M VIDEO/RGB QL01 M38002SFP P501 RESET P901 QL09 XL01 S+6V 8 MHz MAIN SW HC541AF QL02 NM27C256Q QL08 HC541AF QL03 CAT24C16P QL05 MAX232CPE PL005...

  • Page 28: System Microcomputer

    2. SYSTEM MICROCOMPUTER This allows easy maintenance of the system when specifi- cation modification, bug correction, etc. will occur. The system microcomputer QL01 employs an 8 bit micro- Table 5-1 shows the terminal function of the system mi- controller (M38002SFP). crocomputer.

  • Page 29: Power Supply Reset Process

    3. POWER SUPPLY RESET The reset IC (QL04) accepts a clock pulse signal for the watch dog timer which is sent from WDT terminal of the PROCESS microcomputer, determines the microcomputer is in an ab- In the power supply reset process, a watch dog timer normal status due to some reason if the clock signal does (MM1096BS) is used as a power supply reset IC (QL04) not exist for about 1s , and sends a reset signal to the RE-...

  • Page 30: Remote Control Reception Process

    5. REMOTE CONTROL Each remote control signal decoded is mixed through the connectors of PL010 or PL011 and fed to the system mi- RECEPTION PROCESS crocomputer (QL01) through a buffer QL07 (MC74 In the remote control reception process, a remote control HC14AF).

  • Page 31: Status Read Process

    7. STATUS READ PROCESS Fig. 5-6 shows a data fetch timing diagram. QL11 reads panel key status and QL12 does various status. In the status read process, two data fetch ICs, QL11, QL12 Table 5-2 shows the contents of the status read signals and (MC74HC165AF) as shown in Fig.

  • Page 32: On-Screen Display Process

    9. ON-SCREEN DISPLAY PROCESS Fig. 5-8 shows the timing diagram for the on-screen con- trol signals. In the on-screen display process, control signals are sup- plied to the OSD display IC QX43 (mPD6453) through P901, and the OSD display IC generates character display signals at the timing determined by VD, HD and clock sup- plied to the IC separately.

  • Page 33: Video System Control Process

    11. VIDEO SYSTEM CONTROL PROCESS In the video system control process, control signals are supplied to various video system process ICs through P501. Fig. 5-10 shows the I C bus timing diagram and table 5-5 shows the contents of process in each kind of IC. Table 5-5 Contents of process in each kind of IC Part No.

  • Page 34: Panel System Control Process

    12. PANEL SYSTEM CONTROL Fig. 5-11 shows the M62358FP control bus timing diagram, Fig. 5-12 does the CXD2442Q control bus timing PROCESS diagram, Fig. 5-13 does the SYG read mode bus timing The panel system control process supplies various control diagram and Fig.

  • Page 35: Various Display Modes

    13. VARIOUS DISPLAY MODES When the power is turned off by pressing the STANDBY/ ON key, the unit enters the standby status in passing through In this system, various LED display patterns are provided following processes. in relation to the display modes shown in Table 5-7. Op- When the lamp power is turned off, STANDBY/ON erations from AC on to power on and power off will be LED turns on in orange.

  • Page 36: Applicable Signal

    14. APPLICABLE SIGNAL In the user mode, the signal line number is detected to al- low the separate adjustment in the VGA system (basically Quite a signals are used as the applicable signals in the effective for line number of 480/400/350 lines) and SVGA preset mode (standard value) as shown in table 5-10.

  • Page 37: Rs-232C Control Method

    15. RS-232C CONTROL METHOD Table 5-9 RS-232C connection signals Pin No. Signal name Signal content Signals are connected to the RS-232C connector in a straight Receive data format as shown in Table 5-9 RS-232C connection signals. Transmit data This is because a crossing connection is provided inside Data terminal ready the unit.
  • Page 38 Table 5-11 RS-232C command list Remote control Item Display Panel key Command Content STANDBY/ON STANDBY/ON Power supply ON Power supply STANDBY/ON STANDBY/ON Power supply OFF INPUT INPUT Video input Input switch INPUT INPUT RGBinput INPUT INPUT Camera input VOL/ADJ + VOL/ADJ + Volume UP Volume...

  • Page 39: Digital Circuit

    SECTION VI DIGITAL CIRCUIT...

  • Page 40: Digital Circuit Operation

    1. DIGITAL CIRCUIT OPERATION 1-1. Display Mode This unit uses a liquid crystal panel with 832 x 624 pixels. In the digital circuit, the following operations are carried Basically, the effective pixel number (scanning line num- out; video signal double speed conversion/enlargement pro- ber) in the vertical direction is specified as the display pixel cess (NTSC signal), sync generation/Various kinds of tim- number in the vertical direction and the display pixel num-...

  • Page 41: Rgb Signal Input

    1-2. RGB Signal Input Fig. 6-2 shows the flow of timing signals when RGB sig- nals are input. PCLK input to QX45 is a sampling clock as When the RGB signals are input, sync generation, various shown in Fig. 6-2. The oscillation range of the VCO com- kinds of timing signals generation for liquid crystal panel posing of PLL (1) is 40 ~ 85 MHz, so the signal is divided driving, and on-screen signal generation are carried out in...

  • Page 42: Ntsc Signal Input

    1-3. NTSC Signal Input In the PLL circuit (2), a clock signal for memory read is generated. In the standard mode, the clock signal gener- NTSC signal is operated in three modes; standard mode to ated is twice as much as the memory write clock signal (4- display a picture with 640 x 480 pixels in the center area of divided clock signal generated in the PLL (1)).

  • Page 43: Circuit Description

    2. CIRCUIT DESCRIPTION The video signal is clamped to fit the reference level of the A/D converter. The clamp is of a pedestal clamp type and 2-1. Clamp Circuit uses the reference level voltage of A/D converter. The ac- tual clamp voltage potential is approx. 1.2V. A/D converter converts the video signal demodulated to RGB signals in the digital signals to perform digital-pro- Fig.
  • Page 44 Table 6-1 CXD1175AM pin function Pin No. Name Functions Output enable terminal OE = "L" level: data enable OE = "H" level: output high impedance 2, 24 DGND Digital GND terminal 3 - 10 D1 - D8 Data otput terminal D1: LSB, D8: MSB 11, 13 Digital power supply terminal Clock input terminal...

  • Page 45: Memory

    2-3. Memory Din 0 Dout 0 Din 1 Dout 1 HM530281RTT-20 (QX19, QX20, QX21) is a 2.5 Mbit Din 2 Dout 2 field memory. The pin configuration of the IC is shown in Din 3 Dout 3 Fig. 6-7 , terminal function in table 6-2 and internal block Din 4 Dout 4 Din 5...
  • Page 46 The IC has a screen applicable address mode which allows The control in each mode is determined by the condition of the access by specifying a horizontal and vertical addresses MODE 0 (pin 20) and MODE 1 (pin 21) when the power is in addition to the one-dimension address mode which works turned on and the modes are set as shown in table 6-3.

  • Page 47: Pld Circuit

    2-4. PLD Circuit These signals of clock signal for read (pin 43), enlarge- ment control signal (pin 44) and field ID signal (pin 2) con- EPM7032LC44-10 is used for PLD (QX41). This PLD is trol the memory are shown in Fig. 6-12. based on CMOS EE-PROM and a device which can be In the standard mode, after resetting the memory, the line written and erased electrically.
  • Page 48 < Input signal > < Output signal > NTSC (Standard) • PAL • SECAM (MAG=L) FIOE=L (ODD FIELD) Operation RESET HOLD HOLD HOLD HOLD RLRS FIOE=H (EVEN FIELD) Operation RESET HOLD HOLD HOLD HOLD RLRS NTSC (Enlargement) (MAG=H) FIOE=L (ODD FIELD) Operation RESET HOLD...

  • Page 49: D/A Converter

    2-5. D/A Converter MB40958PF is a 8-bit/3ch bi-polar D/A converter which works at a conversion rate of 60 M sample/s. The pin con- 48 47 46 45 44 43 42 41 40 39 38 37 figuration of the IC is shown in Fig. 6-13, the pin functions CLKR ROUT1 are in table 6-6 and its internal block diagram is in Fig.
  • Page 50 CLKR (MSB) Master slave (LSB) (MSB) Master slave (LSB) (MSB) Master slave (LSB) Ref Resistance Amp. Ref. voltage 1 Ref. voltage 2 0.6xV D.GND A.GND COMP ROUT1 ROUT2 Fig. 6-14 MB40958PF internal block diagram LX14 CX38 TEM2011T 25V 6.8 Clock R signal CX39 CX36...

  • Page 51: Memory Control And Sync Process Ic

    2-6. Memory Control and Sync Process IC A clock signal used in the memory read timing control cir- cuit operation can be used by switching the clock signal TC160G54AF1137 (usually called SYG, QX32) is an gate generated in the PLL circuit (1) (divided in four) and the array which carries out the memory control and sync pro- clock signal generated in PLL circuit (2) with the serial cess.

  • Page 52: Pll Circuit (1)

    2-7. PLL Circuit (1) TLC2933IPW TLC2933IPW is used in the PLL circuit. The pin configu- BIAS ration is shown in Fig. 6-17, the terminal functions are in SUPPLY table 6-7 and the internal block diagram is shown in Fig. 6- CONTROL 18.

  • Page 53: Pll Circuit (2)

    QX52 LX21 MC33078M +5 VD TEM2103T CX62 CX58 CX61 RX82 0.33 0.33 3.3k V BLK RY42 VD-D VD-A ZX15 TEM2026D Clock RBIAS RX77 47 output VCOO VCIN FI-A Inside CY21 FI-B VIHB RX78 330 0.01 PIHB PFDO Outside RX79 330 CY19 ZX16 QX38...
  • Page 54 LX24 CX70 CX71 TEM2103T +5 DV 0.33 0.33 RX88 QX42 3.3k TLC2932IPW VD-D VD-A RBIAS VCOO VCIN FI-A FI-B VIHB PIHB PFDO RX89 RX72 RX87 15k OSC stop signal Fig. 6-22 PLL Circuit (2) circuit diagram Table 6-8 TLC2932IPW pin function Pin No.

  • Page 55: Liquid Crystal Panel Timing Generation Circuit

    2-9. Liquid Crystal Panel Timing Genera- This IC generates all the timing necessary for the liquid tion Circuit crystal panel. The IC operation is controlled by the serial bus and the IC controls the up/down/left/right inversion CXD2442Q (QX45) is a timing generation IC for the liq- and signal mode setting.
  • Page 56 Name Functions TST4 Test terminal (Open when used.) TST5 Test terminal (Connect to GND.) Power supply CKLIM CKI1 input limit input terminal (H: CKI1 input possible, L: impossible) TST6 Test terminal (Open when used.) XCLP1 Pulse 1 output for pedestal clamp (Negative polarity) XCLP2 Pulse 2 output for pedestal clamp (Negative polarity) Pulse output for pre-charge signal...
  • Page 57 Name Functions V clock pulse output V start pulse output TST7 Test terminal (Open when used.) PCG pulse ouptput (Positive polarity) TST8 Test terminal (Open when used.) Up and down inversion identification signal output (H: down, L: up) RSTR Reset read output (For high speed line buffer, Negative polarity) Read clock output (For high speed line buffer) RSTW Reset write output (For high speed line buffer, Negative polarity)
  • Page 58 24 33 48 73 2 12 17 23 32 38 42 52 63 72 CK12 CKLIM CK11 MASTER CLOCK XCLR DIRECT CLEAR CK01 PLL PHASE COMPARATOR H-SYNC HYSNC DETECTOR PLL COUNTER RSTR DECODER V-SYNC SEPARATOR VSYNC RSTW V-RESET PULSE GENERATOR V-CONTROL COUNTER SCTR SCLK...
  • Page 59 LCX016 SVGA 800x600 RGT : H PLLP : LHHHHHLLHLH(LSB) HP : HHHLHLLL(LSB) HDNP : LLLLL(LSB) SHP : LLLLLLL(LSB) HCKP : LLLL(LSB) Loop Counter : 999fh MCK f : 48.00MHz(20.83ns) HSTP : LH(LSB) CLPP : LL(LSB) SHD2/1/0 : L/H/H SH2/1/0 : H/L/H HPOL : L CK : L HR : H HST : H HST : H PCG : H 120fh HSYNC 24fh...
  • Page 60 LCX016 SVGA 800x600 MODE3/2/1 : H/L/L MODE : H DWN : H VP : LLHLLLHH(LSB) MBK2/1/0/B/A : H/H/H/L/L VVPO : L FRP1/0 : H/H DSP : H PC98 : H VSYNC HSYNC (BLK) (1H reverse) XCLP1 XCLP2 (1F reverse) FLDO Note : DWN : VST is inverted at L.

  • Page 61: On-Screen Character Generation Circuit

    2-10. On-screen Character Generation Cir- cuit BUSY HSYNC µPD6453GT (QX43) is an IC for the on-screen character VSYNC generation function. The pin configuration of the IC is shown in Fig. 6-27, the terminal functions are in table 6-10 DATA and the internal block diagram is in Fig. 6-28. The RGB signals for on-screen character display output from pins 12, 13 and 14 and the on-screen switching signal output from pin 15 are developed from the digital circuit and su-...
  • Page 62 Table 6-10 µPD6453GT pin function Pin No. Name Terminal Name Function Power supply terminal Power supply ( 5V) terminal Connect to system GND. Clear terminal at power on. Set to L to H when power is turned on. Power on clear terminal VRAM lump-release start-up and test mode release operations are carried out.

  • Page 63: Video Signal Process Circuit

    SECTION VII VIDEO SIGNAL PROCESS CIRCUIT...

  • Page 64: Outline

    1. OUTLINE 1-3. RGB Signal Amplification Circuit Block 1-1. Circuit Configuration The RGB input signals are gain-adjusted in passing through The video signal process circuit consists of a video signal the RGB process IC after the signals are switched to the demodulation (NTSC, PAL, SECAM), RGB signal (VGA, RGB demodulated video signal, and then the RGB input SVGA) amplification and audio signal amplification cir-...

  • Page 65: Input/Output Signal Switch Circuit

    2. INPUT/OUTPUT SIGNAL 2-2-3. Camera Signal SWITCH CIRCUIT The video signal sent from the camera section is supplied as Y/C signal and input to pins 16 and 18. The I/O signal switch circuit selects signals (video and au- The video signal finally selected is output from pins 34 (C) dio ) entered and feeds them to later stages and each output and 36 (Y) respectively and supplied to the signal process- terminal.
  • Page 66 PIP applied : 42Pin Non-PIP applied : [ ] terminals are deleted Det select Det in - 6 dB V1 in V2 in V out 1 6 dB TV in 6 dB S1 (Y/V) in [V out 2] 6 dB S2 (Y/V) in Y out YI in...

  • Page 67: Video Demodulation Block

    3. VIDEO DEMODULATION Table 7-1 Terminal function of TC9090AN BLOCK Name Function 3-1. YC Separation Circuit ADC bias REFL ADC GND This circuit separates Y and C signals from a composite ADIN Video input video signal. Fig. 7-4 shows the pin configuration of ADC V TC9090AN and Fig.

  • Page 68: Video/Color Circuit

    3-2. Video/Color Circuit Fig. 7-7 shows the pin configuration of TDA9141 and Fig. 7-8 shows the block diagram of TDA9141. Fig. 7-9 shows The video/color circuit consists of two ICs, TDA9141 (NTSC/ the pin configuration of TDA4665T and Fig. 7-10 shows PAL/SECAM DECODER), TDA4665T (BASEBAND DE- the block diagram of TDA4665T.

  • Page 69: Luminance (Y) Signal Process Circuit

    TDA9141 has two input terminals for the composite video/ Table 7-2 Terminal function of TDA4665T Y signal (pin 25) and C signal (pin 26), and each of the Pin No. Name Function signals is automatically identified through I C-BUS con- +5V power supply for digital block trol.

  • Page 70: Color Signal Process Circuit

    3-4. Color Signal Process Circuit The color signal is level adjusted in the ACC (automatic MED757 color control) circuit, corrected in passing through a band GND1 pass circuit in the NTSC/PAL system, or a bell filter cor- rection is carried out in the SECAM system, and then en- SAND ters the color demodulation circuit.

  • Page 71: Rgb Demodulation

    Sand castle V = 5V to 8V 100nF 100nF pulse SAND CASTLE PULSE C EBUS C EBUS RECEIVERS Y delay DETECTOR Sand castle Coring Peaking GENERATION 5V / 12V on / off frequency BK.H+V DELAY TIME CONTROL V REF CORING 5 MHz BLACK LEVEL -0.5...
  • Page 72 Table 7-4 Terminal function of TDA4780 Name Function Name Function High speed switch 2 input Equal beam current limit input Red input 2 Memory capacitor for peak limit Memory capacitor for leakage current Green input 2 compensation Blue input 2 Memory capacitor for peak dark POST Power supply voltage...

  • Page 73: Audio Circuit

    3-7. Audio Circuit 4. RGB SIGNAL PROCESS CIRCUIT Fig. 7-15 shows the audio circuit block diagram. 4-1. RGB Signal SW Section Signal path from the Q200 to the LINE OUT terminal is: The RGB signals are entered from a high density D-SUB Q200 Æ...

  • Page 74: Video/Rgb Signal Sw Section

    4-2. Video/RGB Signal SW Section VIDEO BUFFER SIGNAL Q520 Fig. 7-17 shows a block diagram of the video/RGB SW Q525 Q530 section. The video signal demodulated in R, G and B sig- nals and the RGB signals input from D-SUB 15P are switched by each analog switch for RGB.

  • Page 75: Microcomputer Interface

    4-4. Microcomputer Interface Table 7-6 Q540 (CXA1315M) Fig. 7-19 shows a block diagram of the peripheral circuit Pin 3 R sub contrast of microcomputer interface circuit. Each kind of control Pin 4 G sub contrast such as signal SW, etc. is carried out by DAC Q540 Pin 5 B sub contrast (CSA1315M) which in turn controlled by I...
  • Page 76 Table 7-7 Q537 (M52346SP) Input status Q543 (CXA1315) Pin 6: HD. COMP Pin 8: VD SW0 (#2) SW1 (#1) SW2 (#9) SW3 (#0) HD. COMP. (POS.) HD. COMP. (POS.) VD (POS.) HD. COMP. (POS.) VD (NEG.) HD. COMP. (NEG.) HD. COMP. (NEG.) VD (POS.) HD.HD.

  • Page 77: Ccd Camera Circuit

    SECTION VIII CCD CAMERA CIRCUIT...

  • Page 78: Outline

    1. OUTLINE The color signal (S1, S2) also enters the process IC (QL02) in the same way as the luminance signal. The camera section of the unit employs the color board The color difference signal (R – Y, B – Y) is generated by camera with 3 times zoom lens.
  • Page 79 EE To PJ01, Pin 5 QJ04 QJ15 QJ13 QJ01 SLICE OPT, LPF LENS QJ03 ZJ01 8fsc QJ02 V.DRIVER QJ05 QL08 QJ14 To PJ02, Pin 2 ZL01 QL04 ZL03 ZL02 QL03 To PJ02, Pin 4 ZL04 H.AP TPL5 QL07 V.AP SET IUP NTSC QL15 QL01...

  • Page 80: Fluorescent Lamp Inverter Circuit

    SECTION IX FLUORESCENT LAMP INVERTER CIRCUIT...

  • Page 81: Operating Description

    1. OPERATING DESCRIPTION CM05 prevents a rapid increase of the collector current of QM03 before the fluorescent lamp turns on. The base current at start-up passes through QM02, RM04 Also, RM04 is a protective posistor to prevent QM03 from – RM06 and then flows into the base of QM03. QM02 generating temperature more than 120°C.

  • Page 82: Troubleshooting

    CM04 is a capacitor to stabilize the fluorescent lamp dis- 70 kHz charging current. After the discharging starts, CM04 lim- its the flow of the current with the reactance of CM04 QM03 (XC = 1/wc). Collector Before the fluorescent lamp turns on, the collector pulse voltage 1.5A of QM03 is 70 –...
  • Page 84 TOSHIBA AMERICA CONSUMER PRODUCTS, INC. NATIONAL SERVICE DIVISION 1420-B TOSHIBA DRIVE LEBANON, TENNESSEE 37087...

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