Sanyo PLV-HD10 Service Manual page 97

Control Port Functions
Pin No. Name
121
Ptm4/Pint4/Rdet/USB_TxD-
122
Reserve/USB1d_SUSPEND
123
USB1_ovr_crnt/USBF_VBUS
124 USB2_ovr_crnt
125 RTS2/USB1d_TXENL
126 PTE[2]/USB1_pwr_en
127 PTE[1]/USB2_pwr_en
128 CKE/PTK[5]
129 RAS3/PTJ[0]
130 Reserve/PTJ[1]
131 Reserve/CAS/PTJ[2]
132 VssQ
133 Reserve/PTJ[3]
134 VccQ
135 Reserve/PTJ[4]
136 Reserve/PTJ[5]
137 Vss
138 PTD[5]/CL1
139 Vcc
140 PTD[7]/DON
141 PTE[6]/M_DISP
142 PTE[3]/FLM
143 PTE[0]/TDO
144 PCC0RESET/DRAK0
145 PCC0DRV/DACK0
146 WAIT
147 RESETM
148 ADTRG/PTH[5]
149 IOIS16/PTG[7]
150 ASEMD0
151 PTG[5]/ASEBRKAK
152 PTG[4]
153
PCC0BVD2/PTG[3]/AUdata[3]
154
PCC0BVD1/PTG[2]/AUdata[2
155 Vss
156
PCC0CD2/PTG[1]/AUDATA[1]
157 Vcc
158
PCC0CD1/PTG[0]/AUDATA[0]
159 VssQ
160 PTF[7]/PINT[15]/TRST
161 VccQ
162 PTF[6]/PINT[14]/TMS
163 PTF[5]/PINT[13]/TDI
164 PTF[4]/PINT[12]/TCK
165 PTF[3]/PINT[11]/Reserve
166 PCCREG/PTF[2]/Reserve
167 PCC0VS1/PTF[1]/Reserve
168 PCC0VS2/PTF[0]/Reserve
169 MD0
170 Vcc-PLL1
171 CAP1
172 Vss-PLL1
173 Vss-PLL2
174 CAP2
175 Vcc-PLL2
176
PCC0WAIT/PTH[6]/AUDCK
177 Vss
178 Vcc
179 XTAL
180 EXTAL
181 LCD15/PTM[3]/PINT[10]
Function Name Function
Port_M / Port Interrupt / AFE Ringing Det/ D- Out
Reserve / Transceiver Suspend Status
(USBF_VBUS) USB Function VBUS
(USB2_ovr_crnt) USB Host_2 Over Current Detector
(USB Digital) SCIF RTS / USB Output Enable
(USB1_pwr_en) USB1 Power Control
(USB2_pwr_en) USB2 Power Control
CKE CK Enable (SDRAM)
RAS3 RAS for SDRAM
Reserve / I/O Port_J
CAS CAS for SDRAM
GND Vss for I/O (0V)
POWER_SW2 Power SW for BGA Board
3.3V Vcc for I/O (3.3V)
SCLK Serial Clock Output
SDATA Serial Data Output
GND Vss (0V)
PIXEL_RESET PIXEL Reset Signal
1.9V Vcc (1.9V)
PW_SEL PIXEL 232CSelect
EXP_RESET EXPANDER Reset Signal
USB_RESET USB Reset Signal
TDO [for ICE] Test Data Output
Unused
Unused
WAIT FPGA2 Hardware Wait
RESETM Manual Reset
(Reserve) Analog Trigger / Port_H
(USBF_VBUS_S) USB Function VBUS
ASEMD0 [ICE] ASE Mode
ASEBRKAK [ICE] ASE Break Acknowledge
USB CONECT USB Connection detector
AUDATA[3] [ICE] AUD Data
] AUDATA[2] [ICE] AUD Data
GND Vss (0V)
AUDATA[1] [ICE] AUD Data
1.9V Vcc (1.9V)
AUDATA[0] [ICE] AUD Data
GND Vss for I/O (0V)
TRST [ICE] Test Reset
3.3V Vcc for I/O (3.3V)
TMS [ICE] Test Mode SW
TDI [ICE] Test Data Input
TCK [ICE] Test Clock
Unused
PCCREG / Port_F / Reserve
PCCVS1 / Port_F / Reserve
PCCVS2 / Port_F / Reserve
MD0 Clock Mode Setting [Default:L]
1.9V Vcc for PLL1 (1.9V)
CAP1 Capacitor for PLL1[470pF]
GND Vss for PLL1 (0V)
GND Vss for PLL2 (0V)
CAP2 Capacitor for PLL2[470pF]
1.9V Vcc for PLL2 (1.9V)
AUDCK [ICE] AUD Clock
GND Vss (0V)
1.9V Vcc (1.9V)
(Reserve) X'tal
EXTAL External Clock / X'tal [33.3333MHz]
Unused -
-97-
Polarity I/O
(Open) -
(Open) -
I
I
(Open)
O
O
O
O
(Open)
O
- -
(L= Off / H= On) O
- -
- O
- O
- -
- O
- -
(H: SH, L: PW) O
- O
- O
- O
(Open) -
(Open) -
- I
- I
- -
- I
- I
- O
- I
- O
- O
- -
- O
- -
- O
- -
- I
- -
- I
- I
- I
- O
(Open) -
(Open) -
(Open)
- I
- -
- -
- -
- -
- -
- -
- I
- -
- -
(Open) -
- I
(Open) -