FUNAI BH2-M200 Service Manual page 46

BD/HDD Main 2 Schematic Diagram
BD/HDD MAIN CBA UNIT
CONTINUE
BD/HDD MAIN 9
P-ON+3.3V
4
R6094 R6092
CONTINUE
10K 10K
BD/HDD MAIN 3
XTRST0
3
CONTINUE
BD/HDD MAIN 8
SYS-RESET
Q6092
MMBTRC103SS
(RESET)
CONTINUE
BD/HDD MAIN 9
Q6091
SYS-RESET
MMBTRC103SS
C6090 (RESET)
0.1
CONTINUE
BD/HDD MAIN 6
G-CK54-SUB
ADC-MCLK
IC6040
2
TC74VHCU04FT
(CLOCK GENERATOR)
1 VCC 14
R6044
47
2 13
3 12
R6045
47
4 11
5 10
6 9
7 GND 8
1
G
2 NOTE:
The order of pins shown in this diagram is different from that of actual IC6001.
IC6001 is divided into nine and shown as IC6001 (1/9) ~ IC6001 (9/9) in this BD/HDD Main Schematic Diagram Section.
X6001
R6000
27MHz
10K
R6013 R6011
1.5K 6.8K
R6010 C6011
51K 1
R6012 C6012
6.8K 1
R6093
10K
R6005
47
C6093
0.1
Q6093
MMBTRC103SS
(RESET)
C6092
0.01
C6025
150P
X6021
27MHz
R6033 R6031
1.5K 6.8K
R6030 C6031
51K 1
R6032 C6032
6.8K 1
R6026
47
R6025
47
C6043
0.1
C6042
10P
X6041
R6041
R6042
33.333MHz
220
1M
C6041
10P
R6043
22
H I
C6001 C6005 C6006
150P 0.1 0.1
IC6000
*2
CY22388ZZXC-25
IC6001(2/9)
(CLOCK GENERATOR)
MN2WS0038DP2-B
MAIN MICRO CONTROLLER
/DIGITAL SIGNAL PROCESS
1 16
VCXO
2 VDD 15
SELECT
LOGIC
3 14 B28 ASELIA
4 VDD 13
PLL
5 VDD VSS 12
R6003
47
6 VSS 11 A31 27MCLKA
DIVIDER
7 10 F28 HDCLK
/MULTIPLEXER
R6001
47
8 9
B30 AEXCKA
F27 ASEL0A
C28 VSELA
B29 VCX0-CTL1
A16 XRST
R6090 10K
F17 XSRST
C6022 C6023 C6024
0.1 0.1 0.1
IC6020
CY22388ZZXC-26
(CLOCK GENERATOR)
1 16
VCXO
2 VDD 15
R6034
SELECT
10K
LOGIC
3 14
4 VDD 13
PLL
5 VDD VSS 12
R6021
47
6 VSS 11 E29 27MCLKB
DIVIDER
7 10 F1 54MCLK
/MULTIPLEXER
R6023
47
8 9
R6024
47
R6022
47
C26 ASELIB
R6029 10K
A30 CK74B
E27 ASEL0B
C27 AI1ADCCK
D28 AEXCKB
G27 VCX0-CTL2
A29 NU
A28 33MCLK1
AP2 33MCLK2
J
1-15-11
K L
E4V21SCB2