Terminal Layout; Block Diagram - JVC KS-F160 Service Manual

KS-F160
QQ
3 7 63 1515 0
LC72362N-9920 (IC701):System controller

1.Terminal Layout

24 - 1
25 80
40 64
41 - 64

2.Block diagram

XIN
XOUT
FMIN
AMIN
SNS
VDD
VSS
V-DET
HCTR
TE
L 13942296513
LCTR
HOLD
TEST1
TEST2
PA0
PA1
PA2
PA3
PB0
PB1
PB2
BP3
PC0
PC1
PC2
PC3
PD0
PD1
PD2
PD3
PE0
SCK2/PE1
PO2/PE2
SI2/PE3
PF0
SCK1/PF1
SO1/PF2
SI1/PF3
www
PF0
SCK1/PF1
SO1/PF2
SI1/PF3
1-18
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DIVIDER REFERENCE DIVIDER
1/16, 1/17
PROGRAMMABLE DIVIDER
1/114, 1/124
LATCH
SNSFF
1/2
UNIVERSAL
COUNTER
(20bits)
RAM
512 4bits
BUS
DRIV.
LATCH
BUS
DRIV.
ROM
12K 16bits
LATCH
BUS
DRIV.
ADDRESS DECODER
LATCH
BUS
DRIV.
PROGRAM COUNTER
LATCH
BUS
STACK
DRIV.
LATCH
BUS
DRIV.
x ao
SIO
y
. i
LATCH
BUS
DRIV.
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8
SELECTOR
PHASE
DETECTOR
UNLOCK
F/F
PHASE
DETECTOR
Q Q
3 6 7 1 3
ADDRESS
DECODER
BEEP
BUS
DRIVER
INSTRU-
CTION
DECODER
JUDGE
ALU
u163 ADC
.
2 9 9 4 2 8
E01
E02
SUBPD
SUB
C.P.
EO3
PQ0
LATCH
PP3
LATCH
PP2
BUS
PP1
1 5 0 5 8 2 9 9 4
DRIV.
PP0
PO3
LATCH
PO2
BUS
PO1
DRIV.
PO0
PN3
LATCH
PN2
BUS
PN1
DRIV.
MPX
PN0/BEEP
PM3
LATCH
PM2
BUS
PM1
DRIV.
PM0
PL3
LATCH
PL2
BUS
PL1
DRIV.
PL0
PK3
LATCH
PK2
BUS
PK1/INT1
DRIV.
PK0/INT0
INTERRUPT
PJ3
LATCH
PJ2
BUS
PJ1
DRIV.
PJ0
PI1/ADI5
BUS
DRIV.
PI0/ADI4
m
MPX co
PH3/ADI3
PH2/ADI2
BUS
DRIV.
PH1/ADI1
PH0/ADI0
9 9
2 8 9 9