Advanced Chipset Features - ROHS ITX-i9453 User Manual

BIOS

3.5 Advanced Chipset Features

DRAM Timing Selectable
It refers to the method by which the DRAM timing is selected.
Setting: Manual, By SPD (Default).
CAS Latency Time
It allows CAS latency time in HCLKs as 3, 2.5, 2 and Auto. The system
board designer should set the values in this field, depending on the DRAM
installed. Do not change the values in this field unless you change
specifications of the installed DRAM or CPU.
Setting: 5, 4, 3, 6, Auto (Default).
DRAM RAS# to CAS# Delay
It allows you to insert a delay between the RAS (Row Address Strobe) and
CAS (Column Address Strobe) signals. This delay occurs when the SDRAM
is written to, read from or refreshed. Reducing the delay improves the
performance of the SDRAM.
Setting: 2, 3, 4, 5, 6, Auto (Default).
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