Kenwood TK-390 Service Manual page 21

TK-390
7. Control Circuit
The control unit consists of microprocessor IC406 and its
peripheral circuits. It controls the TX-RX unit and transfers
data to and from the control unit. The CPU (IC406) mainly
performs the following :
1) Switching between transmission and reception by PTT
signal input.
2) Reading channel, frequency, and program data from the
memory circuit.
3) Sending frequency program data to the PLL.
4) Controlling squelch on/off by the pulse signal input from
the squelch circuit.
5) Controlling the audio mute circuit by decode data input.
6) Transmitting encode data (QT, DTQ).
7) Sending serial data to output expander (IC400, IC403,
IC404 and IC405) to control various function in the unit.
7-1. Memory circuit
IC406 has a flash memory with a capacity of 1M bits that
contains the transceiver control program for the CPU and
data such as transceiver channels and operating features.
This program can be easily written from an external de-
vices. Data, such as DTMF memories and operating status,
are programmed into the EEPROM (IC412).
IC406
CPU
Fig. 13 Memory circuit
7-2. CPU clock shift
When the CPU (IC406) 14MHz clock (X400) high fre-
quency (actually the integral double high frequency of 7MHz
because it is halved) is multiplexed with the reception fre-
quency, it becomes an internal beat signal, suppressing the
signal sensitivity. To prevent this, by turning Q407 on, the
clock frequency is shifted (about 4kHz).
(Shift on/off can be set through programming.)
C448
Q407
SW
C447
Fig. 14 CPU clock frequency shift
7-3. Shift register
IC400, 403, 404 and 405 is an interface IC for I/O port
expansion. It is used to expand the CPU (IC406) output
ports.
20
CIRCUIT DESCRIPTION
IC412
EEPROM
IC408,410,411
LATCH ADDRESS
DECODE
FLASH
R428 IC405
4
SHIFT
REGISTER 2
58
X1
57
IC406
X2
CPU
86
Vcc
7-4. D/A converter
IC3 and IC603 is used as a conventional semi-fixed-resis-
tor converter. It sets the following :
1) RX sensitivity
2) Transmission power
3) Modulation level
4) Audio power
5) Frequency
7-5. Key input
It the clock is supplied to CLK terminal when the RES
terminal (CPU pin 70) of the decade counter (IC2) is set to
Low, Q0 to Q7 become High sequentially. Normally, KI1
and KI2 are Low (pulled down). When any key is pressed,
KI1 or KI2 become High. The CPU detects which key is
pressed, according to the voltage of KI1 and KI2 and clock
timing.
TOP SW
Top1
D19
Top2
D20
SIDE SW
Orange
D12
Side1
D13
Side2
D15
IC4 IC5 IC6
TC7SH TC7SH TC7SH
08FU 08FU 08FU
MAND TCONT
OPPTT
D16
Fig. 15 Key input
RESET
CLOCK
CLOCK
CLOCK
INHIBIT
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
CARRY
OUT
Fig. 16 Decade counter timing chart
70
CLK KRST
IC2
69
RES KCK
67
KEY1
D17 D11
1 2 3
KI1
4 5 6
KI2
7 8 9
0 #
*
D18 D14
IC406
CPU
66
KEY2