Kenwood TK-390 Service Manual page 20

4-5. APC circuit
The APC circuit always monitors the current flowing
through the RF power amplifier (IC501) and keeps a con-
stant current. The voltage drop at R35, R37, and R39 is
caused by the current flowing through the RF power ampli-
fier and this voltage is applied to the differential amplifier
(IC7 1/2).
IC7 (2/2) compares the output voltage of IC7 (1/2) with
the reference voltage from IC3, and the output of IC7 (2/2)
controls the VGG of the RF power amplifier to make the
both voltages to same voltage.
The change of power high/low is carried out by the
change of the reference voltage. Q7, Q9, and Q13 are
turned on in transmit and the APC circuit is active. (See Fig-
ure 8)
5. PLL Frequency Synthesizer
The frequency synthesizer consists of the VCXO (X1),
VCO (IC10), PLL IC (IC5) and buffer amplifiers.
The VCXO generates 16.8MHz. The frequency stability is
within 2.0ppm (temperature range of –30 to +60°C). The
frequency tuning and modulation of the VCXO are done to
apply a voltage to pin 1 of the VCXO. The output of the
VCXO is applied to pin 8 of the PLL IC.
The VCO of TK-390 covers the 40MHz spread, setting
frequencies in r1, r2 (receive) and t1, t2 (transmit) with a bias
voltage applied to the –V terminal of the VCO. A zero (0) volt
bias is applied at frequencies lower than r1, t1. Frequencies
r1, t1 through r2, t2 are biased with –3 volts. Frequencies
higher than r2, t2 are biased with –6 volts.
The relation of VCO frequency versus PLL lock voltage is
shown in Figure 11.
The output of the VCO is amplified by the buffer amplifier
(Q3) and routed to the pin 5 of the PLL IC. Also the output of
the VCO is amplified by the buffer amplifier (Q5) and routed
to the next stage according to T/R switch (D7).
The PLL IC consists of a prescaler, fractional divider, ref-
erence divider, phase comparator, charge pump. This PLL
IC is fractional-N type synthesizer and performs is the 40 or
50kHz reference signal which is eighth of the channel step
(5 or 6.25kHz). The input signal from the pins 1 and 5 of the
PLL IC is divided down to the 40 or 50kHz and compared at
phase comparator. The pulsed output signal of the phase
comparator is applied to the charge pump and transformed
into DC signal in the loop filter (LPF). The DC signal is ap-
plied to the pin 4 of the VCO and locked to keep the VCO
frequency constant.
PLL data is output from DT (pin21), CLK (pin 22) and LE
(pin 20) of the microprocessor (IC406). The data are input to
the PLL IC when the channel is changed or when transmis-
sion is changed to reception and vice versa. A PLL lock con-
dition is always monitored by the pin 28 (UL) of the micro-
processor. When the PLL is unlocked, the UL goes low.
CIRCUIT DESCRIPTION
6. Power Supply Circuit
minal connected to the TX-RX unit. After passing through
the power switch power supply (SB) is applied to the two
AVR ICs, and AVR circuit.
supplies 5V (5M) to the common circuit.
to the TX circuit and the RX circuit. 5C is common 5V and
output when SAVE is not set at off. 5R is 5V for reception
and output during reception. 5T is 5V for transmission and
output during transmission.
CLK
STB1
IC6 IC10
–V
–VC VCO
CV
LPF BUFF
IC5
5
14
X1
PLL
VCXO
28 8
UL
CPU
DT,CLK,LE
IC406
Fig. 10 PLL block diagram
r1 r2
t1 t2
Fig. 11 CV voltage vs frequency
Battery +B is supplied via a 3A fuse from the battery ter-
IC401 supplies 5V (5CM) to the control circuit. IC402
AVR circuit (Q400, Q402, Q405, Q406) supplies voltage
5V REG
SB IC402 5M
TK11250BM
SW
Q401
UPA572T
Q400,405 : UMG3N x 2
5TC 5CC
SHIFT
5RC
REGISTER 1
DT
IC400
BU4094BCFV
5M OE DAT
Fig. 12 Power supply circuit
TK-390
Q5 D7
To
BUFF SW drive
amp
To mixer
Q3
IC3
FC
TO
IC604
Frequency
(MHz)
512
SW 5T
Q402 : MP5A02
5C
DTA
5R
123JE
SW
Q406
19