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Phytec phyCORE-LPC3250 Manuals
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Phytec phyCORE-LPC3250 manuals available for free PDF download: Hardware Manual, Quick Start Instructions
Phytec phyCORE-LPC3250 Hardware Manual (139 pages)
System on Module and Carrier Board
Brand:
Phytec
| Category:
Computer Hardware
| Size: 3 MB
Table of Contents
Table of Contents
2
List of Tables
4
Conventions, Abbreviations and Acronyms
7
Table 1-1. Abbreviations and Acronyms Used in this Manual
7
Preface
9
Part I: PCM-040/Phycore-LPC3250 System on Module
10
1 Introduction
11
Block Diagram
13
Fig. 1-1. Phycore-LPC3250 Block Diagram
13
View of the Phycore-LPC3250
14
Fig. 1-2. Top View of the Phycore-LPC3250 (Controller Side)
14
Fig. 1-3. Bottom View of the Phycore-LPC3250 (Connector Side)
15
2 Pin Description
16
Fig. 2-1. Pin-Out of the Phycore-Connector (Top View, with Cross Section Insert)
17
Table 2-1. Pin Descriptions, Phycore-Connector X2, Row a
17
Table 2-2. Pin Descriptions, Phycore-Connector X2, Row B
19
Table 2-3. Pin Descriptions, Phycore-Connector X2, Row C
21
Table 2-4. Pin Descriptions, Phycore-Connector X2, Row D
24
Fig. 3-1. Jumper Locations (Controller Side)
28
3 Jumpers
28
Fig. 3-2. Jumper Locations (Connector Side)
29
Table 3-1. Jumper Settings
29
Fig. 3-3. Default Jumper Settings (Controller Side)
31
Fig. 3-4. Default Jumper Settings (Connector Side)
32
4 Power
33
Analog-To-Digital Converter Power (VCC_AD_EXT)
33
Primary System Power (VCC)
33
Secondary Battery Power (VBAT)
33
On-Board Voltage Regulators
34
Primary 1.2V and 1.8V Supplies (U23)
35
Table 4-1. U23 1.2V/1.8V Primary Voltage Regulator Jumper Settings
35
SDIO Controller Power (VCC_SDIO)
34
Fig. 4-1. Phycore-LPC3250 On-Board Powering Scheme
35
Adjustable Core Voltage Supply (U27)
36
SDRAM and RTC Supplies (U22)
36
Selecting Shunt Resistors for Current Measurements
36
Table 4-2. U22 RTC/SDRAM Voltage Regulator Jumper Settings
36
Table 4-3. Primary System Supervisor Reset Thresholds
37
Table 4-4. Sleep System Supervisor Reset Thresholds
37
Voltage Supervisor (U16, U17)
37
5 Deep Sleep
39
Fig. 5-1. Typical Phycore-LPC3250 Sleep Enabled Powering Scheme
39
6 External RTC (U26)
41
7 External Watchdog
42
8 System Configuration and Booting
43
Boot Process and Boot Modes
43
Fig. 8-1. Small Page SLC NAND Flash Structure
45
Stage 1 Loader
46
Boot Sequence
47
9 System Memory
48
NAND Flash (U8)
48
Sdram (U10, U11)
48
Table 9-1. Valid SDRAM Memory Address Ranges
48
Table 9-2. NAND Flash Write Protection Via Jumper J5
48
Eeprom (U9)
49
NOR Flash (U12, U13)
49
NOR Vs. NAND
49
Table 9-3. Valid nor Flash Memory Address Ranges
49
Table 9-4. EEPROM Configuration Struct Dramcfg Field Format
50
Table 9-5. EEPROM Configuration Struct Syscfg Field Format
50
Memory Map
51
Table 9-6. Phycore-LPC3250 Memory Map
51
10 Serial Interfaces
52
Transceiver (U25)
52
Ethernet PHY (U6)
52
Table 10-1. UART 1/UART 5 TTL and RS-232 Level Signals
52
Configuring the PHY Operating Mode (J7, J8, J9)
53
Fig. 10-1. Ethernet PHY Disconnection Resistors
53
Table 10-2. Ethernet PHY Operating Mode Selection
54
USB OTG Transceiver (U24)
54
Table 10-3. Applicable USB Operating Mode Connectors
55
11 SDIO Controller (U14)
56
Table 11-1. SDIO Controller to LPC3250 Signal Mapping
56
Table 11-2. SDIO Controller Interface Signals
57
12 Debug Interface (X1)
58
Fig. 12-1. JTAG Interface X1 (Controller Side)
58
13 Bus Buffers (U1, U2, U3, U4, U5)
59
Table 13-1. Buffered Memory Bus Signal Mapping
59
Table 13-2. Buffered Memory Bus Map
59
Buffered Memory Bus Voltage Select (J21)
60
Fig. 14-1. Phycore-LPC3250 Physical Dimensions
61
Table 14-1. Technical Specifications
61
14 Technical Specifications
61
Table 14-2. Static Operating Characteristics
62
15 Hints for Handling the Phycore-LPC3250
63
16 Component Placement Diagrams
64
Fig. 16-1. Phycore-LPC3250 Component Placement (Controller Side)
64
Fig. 16-2. Phycore-LPC3250 Component Placement (Connector Side)
65
Part II: PCM-967/Phycore-LPC3250 Carrier Board
66
17 Introduction
67
Fig. 17-1. Phycore-LPC3250 Carrier Board Overview of Connectors and Interfaces
67
18 Overview of Peripherals
68
Table 18-1. Connectors and Headers
68
Table 18-2. Description of the Buttons and Switches
69
Table 18-3. Description of Leds
69
Table 18-4. Description of Potentiometers
69
Fig. 19-1. Jumper Locations and Default Settings
70
19 Jumpers
70
Fig. 19-2. Typical Jumper Pad Numbering Scheme (Removable Jumpers)
71
20 Phycore-LPC3250 SOM Connectivity
74
Table 19-1. Jumper Settings
71
Fig. 20-1. Phycore-LPC3250 SOM Connectivity to the Carrier Board
74
21 Power
75
Fig. 21-1. Powering Scheme
75
Wall Adapter Input
77
Fig. 21-2. Powering Scheme Block Diagram
77
Lithium-Ion Battery
78
Power over Ethernet (Poe)
78
Table 21-1. Possible Ethernet PSE Options
78
Battery Charging Circuit
79
Supply (U9)
79
Buck-Boost Supply (U21)
80
Current Measurement
80
Power Path Controller
80
Supply (U10)
80
22 JTAG Connectivity
81
Fig. 22-1. JTAG Probe Connectivity to the LPC3250
81
Table 22-1. LPC3250 JTAG Connector X12 Pin Descriptions
81
Table 22-2. Compatible JTAG Probes for the Phycore-LPC3250 Carrier Board
82
23 Deep Sleep Circuit
84
Fig. 23-1. Deep Sleep Jumpers and Power Button
84
Fig. 23-2. Deep Sleep Circuit Block Diagram
85
Fig. 23-3. Deep Sleep State Diagram
87
Deep Sleep Supply (U11)
88
24 Audio Interface
89
Fig. 24-1. Audio Interface Connectors and Jumpers
89
25 Ethernet Connectivity
91
Fig. 25-1. Ethernet Interface Connectors and Jumpers
91
26 USB Connectivity
93
Fig. 26-1. USB Interface Connectors and Jumpers
93
27 LCD Connectivity
95
Fig. 27-1. LCD Interface Connectors and Jumpers
95
Fig. 27-2. LCD BLUE Signal Mapping in 24-Bit Mode with a 24-Bit LCD
96
Fig. 27-3. LCD BLUE Signal Mapping in 16-Bit Mode with an 18-Bit LCD
96
Table 27-1. LPC3250 LCD Port to Buffered CPLD Signal Mapping
98
Table 27-2. LCD Mode Jumper Summary (JP48, JP49, JP50)
99
Fig. 28-1. GPIO Expansion Connector
100
28 GPIO Expansion Connector
100
Fig. 29-1. RS-232 Interface Connectors and Jumpers
101
Fig. 29-2. DB-9 RS-232 Connectors P1A and P1B Pin Numbering
102
Table 29-1. Connector P1A (UART5) Pin Descriptions
102
Table 29-2. Connector P1B (UART3 and UART2) Pin Descriptions
102
Fig. 29-3. UART3/UART2 Header Connector X13 Pin Numbering
103
Table 29-3. UART3/UART2 Header Connector X13 Pin Descriptions
103
Table 29-4. Configuring DB-9 Connector P1B for UART3 or UART2 Operation
104
Fig. 30-1. SD/MMC Interface Connectors and Jumpers
106
29 Connectivity
101
30 SD/MMC Connectivity
106
Fig. 31-1. SDIO Interface Connectors and Jumpers
108
Table 31-1. SDIO Easy Access Header Connector X23 Signal Descriptions
109
Fig. 32-1. Keyboard Interface Connector and Dip Switches
111
31 SDIO Connectivity
108
32 Keyboard Connectivity
111
Table 32-1. Dip Switch S5 Positions and Associated Signals
112
Table 32-2. Dip Switch S6 Positions and Associated Signals
112
Table 32-3. Ethernet/Keyboard Easy Access Header Connector X11 Signal Descriptions
112
Fig. 33-1. User Buttons and Jumpers
114
33 User Buttons
114
Fig. 34-1. User Leds and Jumpers
116
34 User Leds
116
35 User ADC Potentiometer
118
Fig. 35-1. User ADC Potentiometer and Jumper
118
36 Boot Mode Selection
119
Fig. 36-1. Boot Mode Selection Jumper
119
37 System Reset Button
120
Fig. 37-1. System Reset Button
120
38 Watchdog Circuit
121
Fig. 38-1. Watchdog Enable Jumper
121
Part III: PCM-988/GPIO Expansion Board
122
39 Introduction
123
Fig. 39-1. PCM-988/GPIO Expansion Board and Patch Field
123
Table 39-1. Signals Removed from the GPIO Expansion Connector
124
40 System Signal Mapping
125
Table 40-1. System Signal Mapping
125
41 Memory Bus Signal Mapping
126
Table 41-1. Memory Bus Signal Mapping
126
42 LCD Signal Mapping
128
Table 42-1. LCD Signal Mapping
128
Table 43-1. UART Signal Mapping
129
43 UART Signal Mapping
129
44 I²C Signal Mapping
130
Table 44-1. I²C Signal Mapping
130
45 GPIO Signal Mapping
131
Table 45-1. GPIO Signal Mapping
131
Table 46-1. USB Signal Mapping
132
46 USB Signal Mapping
132
47 SSP Signal Mapping
133
Table 47-1. SSP Signal Mapping
133
48 I²S Signal Mapping
134
Table 48-1. I²S Signal Mapping
134
49 Power Signal Mapping
135
Table 49-1. Power Signal Mapping
135
Revision History
136
Table 50-1. Revision History
136
Index
137
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Phytec phyCORE-LPC3250 Quick Start Instructions (41 pages)
Rapid Development Kit
Brand:
Phytec
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
3
Introduction
4
Rapid Development Kit Documentation
4
Professional Support Packages Available
4
Overview of this Quickstart Instruction
5
Conventions Used in this Quickstart
5
System Requirements
7
Install the PHYTEC Kit CD
7
Microsoft Visual Studio 2005 Development Tool Chain
8
Getting Started
10
Installation Sequence
10
Installing Visual Studio 2005
11
Installing Windows Embedded CE 6.0 Platform Builder
12
Installing Service Packs and Windows Embedded CE6.0 Platform Builder R2
13
Install Windows Embedded CE 6.0 Qfe's
13
Installing Microsoft Active Sync 4.5
13
Installing Phycore-LPC3250 SDK
13
Boot Windows Embedded CE os on the Phycore®-LPC325011
14
Establishing an Active Sync Connection
15
2.10 Downloading Application Code with Active Sync
16
2.11 Downloading Application Code with Visual Studio 2005
17
Getting more Involved
20
Creating a New Project
20
Modifying the Source Code
23
Building the Project
25
Debugging
26
40 Min
26
Starting the Debugger
26
Visual Studio 2005 Debug Features
28
Using the Visual Studio 2005 Debug Features
29
Running, Stopping and Resetting
29
Changing Target Settings for the "Executable Version
30
Building an os Image
31
Download and Install the Phycore-LPC3250 Binary BSP
31
Open the Osdesign
32
Build the Image
32
Download an Image Using Visual Studio
33
Appendix A Install the Bootloader (Eboot.nb0) from SD Card
37
Appendix B Install an Image (Nk.bin) from SD Card
39
Phytec phyCORE-LPC3250 Quick Start Instructions (32 pages)
Rapid Development Kit for Linux
Brand:
Phytec
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table of Contents
3
Introduction
4
Rapid Development Kit Documentation
4
Professional Support Packages Available
4
Overview of this Quickstart Instruction
4
Conventions Used in this Quickstart
5
Kit Contents
5
System Requirements
6
The PHYTEC Kit CD
6
Getting Started
7
Rapid Development Kit Setup
7
Booting the Pre-Built Images
8
Getting more Involved
10
Installing the Linux Target Image Builder (LTIB)
10
Building U-Boot, the Linux Kernel, and Root File System
12
Setting up TFTP
14
Setting up NFS
15
Overview of the Boot Process
16
Placing U-Boot into NAND Flash
17
Configuring U-Boot to Boot Linux over TFTP
19
Placing the Kernel into NAND Flash
20
Placing the Root File System into NAND Flash
21
Placing the Root File System on an SD/MMC Card
23
Building Custom Images
26
Building Openssh and the Apache Web Server
26
Testing Openssh
27
Testing the Apache Web Server
27
Adding Your Own Packages
29
Appendix A: Helpful Hints and Tips
30
Where to Find more Information
30
NAND Flash Layout
30
Using DHCP Instead of a Static IP
31
Enabling Ethernet in the Provided Images
32
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